Ethernet MAC Peripheral

EMAC (AT91S_EMAC) 0xFFFBC000 (AT91C_BASE_EMAC)

Periph ID AIC	Symbol	Description
24	(AT91C_ID_EMAC)	Ethernet MAC

Signal	Symbol	PIO controller	Description
ERXER	(AT91C_PA14_ERXER )	PIOA Periph: A Bit: 14	Ethernet MAC Receive Error
ERX0	(AT91C_PA12_ERX0 )	PIOA Periph: A Bit: 12	Ethernet MAC Receive Data 0
ERX1	(AT91C_PA13_ERX1 )	PIOA Periph: A Bit: 13	Ethernet MAC Receive Data 1
ETXEN	(AT91C_PA8_ETXEN )	PIOA Periph: A Bit: 8	Ethernet MAC Transmit Enable
EMDIO	(AT91C_PA16_EMDIO )	PIOA Periph: A Bit: 16	Ethernet MAC Management Data Input/Output
ETX0	(AT91C_PA9_ETX0 )	PIOA Periph: A Bit: 9	Ethernet MAC Transmit Data 0
ETX1	(AT91C_PA10_ETX1 )	PIOA Periph: A Bit: 10	Ethernet MAC Transmit Data 1
ECRS_ECRSDV	(AT91C_PA11_ECRS_ECRSDV)	PIOA Periph: A Bit: 11	Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
EMDC	(AT91C_PA15_EMDC )	PIOA Periph: A Bit: 15	Ethernet MAC Management Data Clock
ETXCK_EREFCK	(AT91C_PA7_ETXCK_EREFCK)	PIOA Periph: A Bit: 7	Ethernet MAC Transmit Clock/Reference Clock

Function	Description
AT91F_EMAC_CfgPIO	Configure PIO controllers to drive EMAC signals
AT91F_EMAC_CfgPMC	Enable Peripheral clock in PMC for EMAC

EMAC Software API (AT91S_EMAC)

Offset	Field	Description
0x0	EMAC_CTL	Network Control Register
0x4	EMAC_CFG	Network Configuration Register
0x8	EMAC_SR	Network Status Register
0xC	EMAC_TAR	Transmit Address Register
0x10	EMAC_TCR	Transmit Control Register
0x14	EMAC_TSR	Transmit Status Register
0x18	EMAC_RBQP	Receive Buffer Queue Pointer
0x20	EMAC_RSR	Receive Status Register
0x24	EMAC_ISR	Interrupt Status Register
0x28	EMAC_IER	Interrupt Enable Register
0x2C	EMAC_IDR	Interrupt Disable Register
0x30	EMAC_IMR	Interrupt Mask Register
0x34	EMAC_MAN	PHY Maintenance Register
0x40	EMAC_FRA	Frames Transmitted OK Register
0x44	EMAC_SCOL	Single Collision Frame Register
0x48	EMAC_MCOL	Multiple Collision Frame Register
0x4C	EMAC_OK	Frames Received OK Register
0x50	EMAC_SEQE	Frame Check Sequence Error Register
0x54	EMAC_ALE	Alignment Error Register
0x58	EMAC_DTE	Deferred Transmission Frame Register
0x5C	EMAC_LCOL	Late Collision Register
0x60	EMAC_ECOL	Excessive Collision Register
0x64	EMAC_CSE	Carrier Sense Error Register
0x68	EMAC_TUE	Transmit Underrun Error Register
0x6C	EMAC_CDE	Code Error Register
0x70	EMAC_ELR	Excessive Length Error Register
0x74	EMAC_RJB	Receive Jabber Register
0x78	EMAC_USF	Undersize Frame Register
0x7C	EMAC_SQEE	SQE Test Error Register
0x80	EMAC_DRFC	Discarded RX Frame Register
0x90	EMAC_HSH	Hash Address High[63:32]
0x94	EMAC_HSL	Hash Address Low[31:0]
0x98	EMAC_SA1L	Specific Address 1 Low, First 4 bytes
0x9C	EMAC_SA1H	Specific Address 1 High, Last 2 bytes
0xA0	EMAC_SA2L	Specific Address 2 Low, First 4 bytes
0xA4	EMAC_SA2H	Specific Address 2 High, Last 2 bytes
0xA8	EMAC_SA3L	Specific Address 3 Low, First 4 bytes
0xAC	EMAC_SA3H	Specific Address 3 High, Last 2 bytes
0xB0	EMAC_SA4L	Specific Address 4 Low, First 4 bytes
0xB4	EMAC_SA4H	Specific Address 4 High, Last 2 bytesr

EMAC Register Description

EMAC: AT91_REG EMAC_CTL Network Control Register

EMAC AT91C_EMAC_CTL 0xFFFBC000

Network Control Register

Offset	Name	Description
0	EMAC_LB AT91C_EMAC_LB	Loopback. Optional. When set, loopback signal is at high level.
1	EMAC_LBL AT91C_EMAC_LBL	Loopback local. When set, connects ETX[3:0] to ERX[3:0], ETXEN to ERXDV, forces full duplex and drives ERXCK and ETXCK_REFCK with HCLK divided by 4.
2	EMAC_RE AT91C_EMAC_RE	Receive enable. When set, enables the Ethernet MAC to receive data.
3	EMAC_TE AT91C_EMAC_TE	Transmit enable. When set, enables the Ethernet transmitter to send data.
4	EMAC_MPE AT91C_EMAC_MPE	Management port enable. Set to one to enable the management port. When zero, forces MDIO to high impedance state.
5	EMAC_CSR AT91C_EMAC_CSR	Clear statistics registers. This bit is write-only. Writing a one clears the statistics registers.
6	EMAC_ISR AT91C_EMAC_ISR	Increment statistics registers. This bit is write-only. Writing a one increments all the statistics registers by one for test purposes.
7	EMAC_WES AT91C_EMAC_WES	Write enable for statistics registers. Setting this bit to one makes the statistics registers writable for functional test purposes.
8	EMAC_BP AT91C_EMAC_BP	Back pressure. If this field is set, then in half-duplex mode collisions are forced on all received frames by transmitting 64 bits of data (default pattern).

EMAC: AT91_REG EMAC_CFG Network Configuration Register

EMAC AT91C_EMAC_CFG 0xFFFBC004

Offset

Name

Description

EMAC_SPD
AT91C_EMAC_SPD

Speed.
Set to 1 to indicate 100 Mbit/sec. operation, 0 for 10 Mbit/sec. Has no other functional effect.

EMAC_FD
AT91C_EMAC_FD

Full duplex.
If set to 1, the transmit block ignores the state of collision and carrier sense and allows receive while transmitting.

EMAC_BR
AT91C_EMAC_BR

Bit rate.
Optional.

EMAC_CAF
AT91C_EMAC_CAF

Copy all frames.
When set to 1, all valid frames are received.

EMAC_NBC
AT91C_EMAC_NBC

No broadcast.
When set to 1, frames addressed to the broadcast address of all ones are not received.

EMAC_MTI
AT91C_EMAC_MTI

Multicast hash enable
When set multicast frames are received when six bits of the CRC of the destination address point to a bit that is set in the hash register.

EMAC_UNI
AT91C_EMAC_UNI

Unicast hash enable.
When set, unicast frames are received when six bits of the CRC of the destination address point to a bit that is set in the hash register.

EMAC_BIG
AT91C_EMAC_BIG

Receive 1522 bytes.
When set, the MAC receives up to 1522 bytes. Normally the MAC receives frames up to 1518 bytes in length.

EMAC_EAE
AT91C_EMAC_EAE

External address match enable.
Optional.

11..10

EMAC_CLK
AT91C_EMAC_CLK

The system clock (HCLK) is divided down to generate MDC (the clock for the MDIO). To conform with IEEE standard 802.3 MDC must not exceed 2.5 MHz. At reset this field is set to 10 so that HCLK is divided by 32.

Value	Label	Description
0	EMAC_CLK_HCLK_8 AT91C_EMAC_CLK_HCLK_8	HCLK divided by 8
1	EMAC_CLK_HCLK_16 AT91C_EMAC_CLK_HCLK_16	HCLK divided by 16
2	EMAC_CLK_HCLK_32 AT91C_EMAC_CLK_HCLK_32	HCLK divided by 32
3	EMAC_CLK_HCLK_64 AT91C_EMAC_CLK_HCLK_64	HCLK divided by 64

EMAC_RTY
AT91C_EMAC_RTY

Retry test. When set, the time between frames is always one time slot. For test purposes only. Must be cleared for normal operation.

EMAC_RMII
AT91C_EMAC_RMII

When set, this bit enables the RMII operation mode. When reset, it selects the MII mode.

EMAC: AT91_REG EMAC_SR Network Status Register

EMAC AT91C_EMAC_SR 0xFFFBC008

Offset	Name	Description
1	EMAC_MDIO AT91C_EMAC_MDIO	0 = MDIO pin is not set 1 = MDIO pin set
2	EMAC_IDLE AT91C_EMAC_IDLE	0 = PHY logic is idle 1 = PHY logic is running

EMAC: AT91_REG EMAC_TAR Transmit Address Register

EMAC AT91C_EMAC_TAR 0xFFFBC00C

Transmit address register. Written with the address of the frame to be transmitted, read as the base address of the buffer being accessed by the transmit FIFO. Note that if the two least significant bits are not zero, transmit starts at the byte indicated.

EMAC: AT91_REG EMAC_TCR Transmit Control Register

EMAC AT91C_EMAC_TCR 0xFFFBC010

Offset	Name	Description
10..0	EMAC_LEN AT91C_EMAC_LEN	Transmit frame length. This register is written to the number of bytes to be transmitted excluding the four CRC bytes unless the no CRC bit is asserted. Writing these bits to any non-zero value initiates a transmission. If the value is greater than 1514 (1518 if no CRC is being generated), an oversize frame is transmitted. This field is buffered so that a new frame can be queued while the previous frame is still being transmitted. Must always be written in address-then-length order. Reads as the total number of bytes to be transmitted (i.e., this value does not change as the frame is transmitted.) Frame transmis-sion does not start until two 32-bit words have been loaded into the transmit FIFO. The length must be great enough to ensure two words are loaded.
15	EMAC_NCRC AT91C_EMAC_NCRC	No CRC. If this bit is set, it is assumed that the CRC is included in the length being written in the low-order bits and the MAC does not append CRC to the transmitted frame. If the buffer is not at least 64 bytes long, a short frame is sent. This field is buffered so that a new frame can be queued while the previous frame is still being transmitted. Reads as the value of the frame currently being transmitted.

EMAC: AT91_REG EMAC_TSR Transmit Status Register

EMAC AT91C_EMAC_TSR 0xFFFBC014

Offset	Name	Description
0	EMAC_OVR AT91C_EMAC_OVR	Ethernet transmit buffer overrun. Software has written to the Transmit Address Register (ETH_TAR) or Transmit Control Register (ETH_TCR) when bit BNQ was not set. Cleared by writing a one to this bit.
1	EMAC_COL AT91C_EMAC_COL	Collision occurred. Set by the assertion of collision. Cleared by writing a one to this bit.
2	EMAC_RLE AT91C_EMAC_RLE	Retry limit exceeded. Cleared by writing a one to this bit.
3	EMAC_TXIDLE AT91C_EMAC_TXIDLE	Transmitter Idle. Asserted when the transmitter has no frame to transmit. Cleared when a length is written to transmit frame length portion of the Transmit Control register. This bit is read-only.
4	EMAC_BNQ AT91C_EMAC_BNQ	Ethernet transmit buffer not queued. Software may write a new buffer address and length to the transmit DMA controller when set. Cleared by having one frame ready to transmit and another in the process of being transmitted. This bit is read-only.
5	EMAC_COMP AT91C_EMAC_COMP	Transmit complete. Set when a frame has been transmitted. Cleared by writing a one to this bit.
6	EMAC_UND AT91C_EMAC_UND	Transmit underrun. Set when transmit DMA was not able to read data from memory in time. If this happens, the transmitter forces bad CRC. Cleared by writing a one to this bit.

EMAC: AT91_REG EMAC_RBQP Receive Buffer Queue Pointer

EMAC AT91C_EMAC_RBQP 0xFFFBC018

Receive buffer queue pointer. Written with the address of the start of the receive queue, reads as a pointer to the current buffer being used. The receive buffer is forced to word alignment.

EMAC: AT91_REG EMAC_RSR Receive Status Register

EMAC AT91C_EMAC_RSR 0xFFFBC020

Offset	Name	Description
0	EMAC_BNA AT91C_EMAC_BNA	Buffer not available. An attempt was made to get a new buffer and the pointer indicated that it was owned by the processor. The DMA rereads the pointer each time a new frame starts until a valid pointer is found. This bit is set at each attempt that fails even if it has not had a successful pointer read since it has been cleared. Cleared by writing a one to this bit.
1	EMAC_REC AT91C_EMAC_REC	Frame received. One or more frames have been received and placed in memory. Cleared by writing a one to this bit.
2	EMAC_OVR AT91C_EMAC_OVR	Ethernet transmit buffer overrun. Software has written to the Transmit Address Register (ETH_TAR) or Transmit Control Register (ETH_TCR) when bit BNQ was not set. Cleared by writing a one to this bit.

EMAC: AT91_REG EMAC_ISR Interrupt Status Register

EMAC AT91C_EMAC_ISR 0xFFFBC024

Offset	Name	Description
0	EMAC_DONE AT91C_EMAC_DONE	Management done. The PHY maintenance register has completed its operation. Cleared on read.
1	EMAC_RCOM AT91C_EMAC_RCOM	Receive complete. A frame has been stored in memory. Cleared on read.
2	EMAC_RBNA AT91C_EMAC_RBNA	Receive buffer not available. Cleared on read.
3	EMAC_TOVR AT91C_EMAC_TOVR	Transmit buffer overrun. Software has written to the Transmit Address Register (ETH_TAR) or Transmit Control Register (ETH_TCR) when BNQ of the Transmit Status Register (ETH_TSR) was not set. Cleared on read.
4	EMAC_TUND AT91C_EMAC_TUND	Transmit error. Ethernet transmit buffer underrun. The transmit DMA did not complete fetch frame data in time for it to be transmitted. Cleared on read.
5	EMAC_RTRY AT91C_EMAC_RTRY	Transmit error. Retry limit exceeded. Cleared on read.
6	EMAC_TBRE AT91C_EMAC_TBRE	Transmit buffer register empty. Software may write a new buffer address and length to the transmit DMA controller. Cleared by having one frame ready to transmit and another in the process of being transmitted. Cleared on read.
7	EMAC_TCOM AT91C_EMAC_TCOM	Transmit complete. Set when a frame has been transmitted. Cleared on read.
8	EMAC_TIDLE AT91C_EMAC_TIDLE	Transmit idle. Set when all frames have been transmitted. Cleared on read.
9	EMAC_LINK AT91C_EMAC_LINK	Set when LINK pin changes value. Optional.
10	EMAC_ROVR AT91C_EMAC_ROVR	RX overrun. Set when the RX overrun status bit is set. Cleared on read.
11	EMAC_HRESP AT91C_EMAC_HRESP	HRESP not OK. Set when the DMA block sees HRESP not OK. Cleared on read.

EMAC: AT91_REG EMAC_IER Interrupt Enable Register

EMAC AT91C_EMAC_IER 0xFFFBC028

Offset	Name	Description
0	EMAC_DONE AT91C_EMAC_DONE	Management done. The PHY maintenance register has completed its operation. Cleared on read.
1	EMAC_RCOM AT91C_EMAC_RCOM	Receive complete. A frame has been stored in memory. Cleared on read.
2	EMAC_RBNA AT91C_EMAC_RBNA	Receive buffer not available. Cleared on read.
3	EMAC_TOVR AT91C_EMAC_TOVR	Transmit buffer overrun. Software has written to the Transmit Address Register (ETH_TAR) or Transmit Control Register (ETH_TCR) when BNQ of the Transmit Status Register (ETH_TSR) was not set. Cleared on read.
4	EMAC_TUND AT91C_EMAC_TUND	Transmit error. Ethernet transmit buffer underrun. The transmit DMA did not complete fetch frame data in time for it to be transmitted. Cleared on read.
5	EMAC_RTRY AT91C_EMAC_RTRY	Transmit error. Retry limit exceeded. Cleared on read.
6	EMAC_TBRE AT91C_EMAC_TBRE	Transmit buffer register empty. Software may write a new buffer address and length to the transmit DMA controller. Cleared by having one frame ready to transmit and another in the process of being transmitted. Cleared on read.
7	EMAC_TCOM AT91C_EMAC_TCOM	Transmit complete. Set when a frame has been transmitted. Cleared on read.
8	EMAC_TIDLE AT91C_EMAC_TIDLE	Transmit idle. Set when all frames have been transmitted. Cleared on read.
9	EMAC_LINK AT91C_EMAC_LINK	Set when LINK pin changes value. Optional.
10	EMAC_ROVR AT91C_EMAC_ROVR	RX overrun. Set when the RX overrun status bit is set. Cleared on read.
11	EMAC_HRESP AT91C_EMAC_HRESP	HRESP not OK. Set when the DMA block sees HRESP not OK. Cleared on read.

EMAC: AT91_REG EMAC_IDR Interrupt Disable Register

EMAC AT91C_EMAC_IDR 0xFFFBC02C

Offset	Name	Description
0	EMAC_DONE AT91C_EMAC_DONE	Management done. The PHY maintenance register has completed its operation. Cleared on read.
1	EMAC_RCOM AT91C_EMAC_RCOM	Receive complete. A frame has been stored in memory. Cleared on read.
2	EMAC_RBNA AT91C_EMAC_RBNA	Receive buffer not available. Cleared on read.
3	EMAC_TOVR AT91C_EMAC_TOVR	Transmit buffer overrun. Software has written to the Transmit Address Register (ETH_TAR) or Transmit Control Register (ETH_TCR) when BNQ of the Transmit Status Register (ETH_TSR) was not set. Cleared on read.
4	EMAC_TUND AT91C_EMAC_TUND	Transmit error. Ethernet transmit buffer underrun. The transmit DMA did not complete fetch frame data in time for it to be transmitted. Cleared on read.
5	EMAC_RTRY AT91C_EMAC_RTRY	Transmit error. Retry limit exceeded. Cleared on read.
6	EMAC_TBRE AT91C_EMAC_TBRE	Transmit buffer register empty. Software may write a new buffer address and length to the transmit DMA controller. Cleared by having one frame ready to transmit and another in the process of being transmitted. Cleared on read.
7	EMAC_TCOM AT91C_EMAC_TCOM	Transmit complete. Set when a frame has been transmitted. Cleared on read.
8	EMAC_TIDLE AT91C_EMAC_TIDLE	Transmit idle. Set when all frames have been transmitted. Cleared on read.
9	EMAC_LINK AT91C_EMAC_LINK	Set when LINK pin changes value. Optional.
10	EMAC_ROVR AT91C_EMAC_ROVR	RX overrun. Set when the RX overrun status bit is set. Cleared on read.
11	EMAC_HRESP AT91C_EMAC_HRESP	HRESP not OK. Set when the DMA block sees HRESP not OK. Cleared on read.

EMAC: AT91_REG EMAC_IMR Interrupt Mask Register

EMAC AT91C_EMAC_IMR 0xFFFBC030

Important Note: The interrupt is masked (disabled) when the corresponding bit is set. This is non-standard for AT91 products as generally a mask bit set enables the interrupt.

Offset	Name	Description
0	EMAC_DONE AT91C_EMAC_DONE	Management done. The PHY maintenance register has completed its operation. Cleared on read.
1	EMAC_RCOM AT91C_EMAC_RCOM	Receive complete. A frame has been stored in memory. Cleared on read.
2	EMAC_RBNA AT91C_EMAC_RBNA	Receive buffer not available. Cleared on read.
3	EMAC_TOVR AT91C_EMAC_TOVR	Transmit buffer overrun. Software has written to the Transmit Address Register (ETH_TAR) or Transmit Control Register (ETH_TCR) when BNQ of the Transmit Status Register (ETH_TSR) was not set. Cleared on read.
4	EMAC_TUND AT91C_EMAC_TUND	Transmit error. Ethernet transmit buffer underrun. The transmit DMA did not complete fetch frame data in time for it to be transmitted. Cleared on read.
5	EMAC_RTRY AT91C_EMAC_RTRY	Transmit error. Retry limit exceeded. Cleared on read.
6	EMAC_TBRE AT91C_EMAC_TBRE	Transmit buffer register empty. Software may write a new buffer address and length to the transmit DMA controller. Cleared by having one frame ready to transmit and another in the process of being transmitted. Cleared on read.
7	EMAC_TCOM AT91C_EMAC_TCOM	Transmit complete. Set when a frame has been transmitted. Cleared on read.
8	EMAC_TIDLE AT91C_EMAC_TIDLE	Transmit idle. Set when all frames have been transmitted. Cleared on read.
9	EMAC_LINK AT91C_EMAC_LINK	Set when LINK pin changes value. Optional.
10	EMAC_ROVR AT91C_EMAC_ROVR	RX overrun. Set when the RX overrun status bit is set. Cleared on read.
11	EMAC_HRESP AT91C_EMAC_HRESP	HRESP not OK. Set when the DMA block sees HRESP not OK. Cleared on read.

EMAC: AT91_REG EMAC_MAN PHY Maintenance Register

EMAC AT91C_EMAC_MAN 0xFFFBC034

Writing to this register starts the shift register that controls the serial connection to the PHY. On each shift cycle the MDIO pin becomes equal to the MSB of the shift register and LSB of the shift register becomes equal to the value of the MDIO pin. When the shifting is complete an interrupt is generated and the IDLE field is set in the Network Status register.
When read, gives current shifted value.

Offset	Name	Description
15..0	EMAC_DATA AT91C_EMAC_DATA	For a write operation this is written with the data to be written to the PHY. After a read operation this contains the data read from the PHY.
17..16	EMAC_CODE AT91C_EMAC_CODE	Must be written to 10 in accordance with IEEE standard 802.3. Reads as written.
22..18	EMAC_REGA AT91C_EMAC_REGA	Register address. Specifies the register in the PHY to access.
27..23	EMAC_PHYA AT91C_EMAC_PHYA	PHY address. Normally is 0.
29..28	EMAC_RW AT91C_EMAC_RW	Read/write Operation. 10 is read. 01 is write. Any other value is an invalid PHY management frame.
30	EMAC_HIGH AT91C_EMAC_HIGH	Must be written with 1 to make a valid PHY management frame. Conforms with IEEE standard 802.3.
31	EMAC_LOW AT91C_EMAC_LOW	Must be written with 0 to make a valid PHY management frame. Conforms with IEEE standard 802.3.

EMAC: AT91_REG EMAC_FRA Frames Transmitted OK Register

EMAC AT91C_EMAC_FRA 0xFFFBC040

A 24-bit register counting the number of frames successfully transmitted.

EMAC: AT91_REG EMAC_SCOL Single Collision Frame Register

EMAC AT91C_EMAC_SCOL 0xFFFBC044

A 16-bit register counting the number of frames experiencing a single collision before being transmitted and experiencing no carrier loss nor underrun.

EMAC: AT91_REG EMAC_MCOL Multiple Collision Frame Register

EMAC AT91C_EMAC_MCOL 0xFFFBC048

A 16-bit register counting the number of frames experiencing between two and fifteen collisions prior to being transmitted (62 - 1518 bytes, no carrier loss, no underrun).

EMAC: AT91_REG EMAC_OK Frames Received OK Register

EMAC AT91C_EMAC_OK 0xFFFBC04C

A 24-bit register counting the number of good frames received, i.e., address recognized. A good frame is of length 64 to 1518 bytes and has no FCS, alignment or code errors.

EMAC: AT91_REG EMAC_SEQE Frame Check Sequence Error Register

EMAC AT91C_EMAC_SEQE 0xFFFBC050

ETH_SEQE An 8-bit register counting address-recognized frames that are an integral number of bytes long, that have bad CRC and that are 64 to 1518 bytes long.

EMAC: AT91_REG EMAC_ALE Alignment Error Register

EMAC AT91C_EMAC_ALE 0xFFFBC054

ETH_ALE An 8-bit register counting frames that:
- are address-recognized,
- are not an integral number of bytes long,
- have bad CRC when their length is truncated to an integral number of bytes,
- are between 64 and 1518 bytes long.

EMAC: AT91_REG EMAC_DTE Deferred Transmission Frame Register

EMAC AT91C_EMAC_DTE 0xFFFBC058

A 16-bit register counting the number of frames experiencing deferral due to carrier sense active on their first attempt at transmission (no underrun or collision).

EMAC: AT91_REG EMAC_LCOL Late Collision Register

EMAC AT91C_EMAC_LCOL 0xFFFBC05C

An 8-bit register counting the number of frames that experience a collision after the slot time (512 bits) has expired. No carrier loss or underrun. A late collision is counted twice, i.e., both as a collision and a late collision.

EMAC: AT91_REG EMAC_ECOL Excessive Collision Register

EMAC AT91C_EMAC_ECOL 0xFFFBC060

An 8-bit register counting the number of frames that failed to be transmitted because they experienced 16 collisions (64 - 1518 bytes, no carrier loss or underrun).

EMAC: AT91_REG EMAC_CSE Carrier Sense Error Register

EMAC AT91C_EMAC_CSE 0xFFFBC064

An 8-bit register counting the number of frames for which carrier sense was not detected and that were maintained in half-duplex mode one slot time (512 bits) after the start of transmission (no excessive collision).

EMAC: AT91_REG EMAC_TUE Transmit Underrun Error Register

EMAC AT91C_EMAC_TUE 0xFFFBC068

An 8-bit register counting the number of frames not transmitted due to a transmit DMA underrun. If this register is incremented, then no other register is incremented.

EMAC: AT91_REG EMAC_CDE Code Error Register

EMAC AT91C_EMAC_CDE 0xFFFBC06C

An 8-bit register counting the number of frames that are address-recognized, had RXER asserted during reception. If this counter is incremented, then no other counters are incremented.

EMAC: AT91_REG EMAC_ELR Excessive Length Error Register

EMAC AT91C_EMAC_ELR 0xFFFBC070

8-bit register counting the number of frames received exceeding 1518 bytes in length but that do not have either a CRC error, an alignment error or a code error.

EMAC: AT91_REG EMAC_RJB Receive Jabber Register

EMAC AT91C_EMAC_RJB 0xFFFBC074

An 8-bit register counting the number of frames received exceeding 1518 bytes in length and having either a CRC error, an alignment error or a code error.

EMAC: AT91_REG EMAC_USF Undersize Frame Register

EMAC AT91C_EMAC_USF 0xFFFBC078

An 8-bit register counting the number of frames received less that are than 64 bytes in length but that do not have either a CRC error, an alignment error or a code error.

EMAC: AT91_REG EMAC_SQEE SQE Test Error Register

EMAC AT91C_EMAC_SQEE 0xFFFBC07C

An 8-bit register counting the number of frames where pin ECOL was not asserted within a slot time of pin ETXEN being deasserted.

EMAC: AT91_REG EMAC_DRFC Discarded RX Frame Register

EMAC AT91C_EMAC_DRFC 0xFFFBC080

Discarded RX Frame Register ETH_DRFC This 16-bit counter is incremented every time an address-recognized frame is received but cannot be copied to memory because the receive buffer is available.

EMAC: AT91_REG EMAC_HSH Hash Address High[63:32]

EMAC AT91C_EMAC_HSH 0xFFFBC090

Hash address bits 63 to 32

EMAC: AT91_REG EMAC_HSL Hash Address Low[31:0]

EMAC AT91C_EMAC_HSL 0xFFFBC094

Hash address bits 31 to 0

EMAC: AT91_REG EMAC_SA1L Specific Address 1 Low, First 4 bytes

EMAC AT91C_EMAC_SA1L 0xFFFBC098

Unicast address bits 31 to 0

EMAC: AT91_REG EMAC_SA1H Specific Address 1 High, Last 2 bytes

EMAC AT91C_EMAC_SA1H 0xFFFBC09C

Unicast address bits 47 to 32

EMAC: AT91_REG EMAC_SA2L Specific Address 2 Low, First 4 bytes

EMAC AT91C_EMAC_SA2L 0xFFFBC0A0

Unicast address bits 31 to 0

EMAC: AT91_REG EMAC_SA2H Specific Address 2 High, Last 2 bytes

EMAC AT91C_EMAC_SA2H 0xFFFBC0A4

Unicast address bits 47 to 32

EMAC: AT91_REG EMAC_SA3L Specific Address 3 Low, First 4 bytes

EMAC AT91C_EMAC_SA3L 0xFFFBC0A8

Unicast address bits 31 to 0

EMAC: AT91_REG EMAC_SA3H Specific Address 3 High, Last 2 bytes

EMAC AT91C_EMAC_SA3H 0xFFFBC0AC

Unicast address bits 47 to 32

EMAC: AT91_REG EMAC_SA4L Specific Address 4 Low, First 4 bytes

EMAC AT91C_EMAC_SA4L 0xFFFBC0B0

Unicast address bits 31 to 0

EMAC: AT91_REG EMAC_SA4H Specific Address 4 High, Last 2 bytesr

EMAC AT91C_EMAC_SA4H 0xFFFBC0B4

Unicast address bits 47 to 32