| Signal | Symbol | PIO controller | Description |
|---|---|---|---|
| D20 | (AT91C_PC20_D20 ) | PIOC Periph: A Bit: 20 | Data Bus [20] |
| D21 | (AT91C_PC21_D21 ) | PIOC Periph: A Bit: 21 | Data Bus [21] |
| D30 | (AT91C_PC30_D30 ) | PIOC Periph: A Bit: 30 | Data Bus [30] |
| D22 | (AT91C_PC22_D22 ) | PIOC Periph: A Bit: 22 | Data Bus [22] |
| D31 | (AT91C_PC31_D31 ) | PIOC Periph: A Bit: 31 | Data Bus [31] |
| D23 | (AT91C_PC23_D23 ) | PIOC Periph: A Bit: 23 | Data Bus [23] |
| D16 | (AT91C_PC16_D16 ) | PIOC Periph: A Bit: 16 | Data Bus [16] |
| D24 | (AT91C_PC24_D24 ) | PIOC Periph: A Bit: 24 | Data Bus [24] |
| D17 | (AT91C_PC17_D17 ) | PIOC Periph: A Bit: 17 | Data Bus [17] |
| D25 | (AT91C_PC25_D25 ) | PIOC Periph: A Bit: 25 | Data Bus [25] |
| D18 | (AT91C_PC18_D18 ) | PIOC Periph: A Bit: 18 | Data Bus [18] |
| D26 | (AT91C_PC26_D26 ) | PIOC Periph: A Bit: 26 | Data Bus [26] |
| D19 | (AT91C_PC19_D19 ) | PIOC Periph: A Bit: 19 | Data Bus [19] |
| D27 | (AT91C_PC27_D27 ) | PIOC Periph: A Bit: 27 | Data Bus [27] |
| D28 | (AT91C_PC28_D28 ) | PIOC Periph: A Bit: 28 | Data Bus [28] |
| D29 | (AT91C_PC29_D29 ) | PIOC Periph: A Bit: 29 | Data Bus [29] |
| Function | Description |
|---|---|
| AT91F_SDRC_CfgPIO | Configure PIO controllers to drive SDRC signals |
| Offset | Field | Description |
|---|---|---|
| 0x0 | SDRC_MR | SDRAM Controller Mode Register |
| 0x4 | SDRC_TR | SDRAM Controller Refresh Timer Register |
| 0x8 | SDRC_CR | SDRAM Controller Configuration Register |
| 0xC | SDRC_SRR | SDRAM Controller Self Refresh Register |
| 0x10 | SDRC_LPR | SDRAM Controller Low Power Register |
| 0x14 | SDRC_IER | SDRAM Controller Interrupt Enable Register |
| 0x18 | SDRC_IDR | SDRAM Controller Interrupt Disable Register |
| 0x1C | SDRC_IMR | SDRAM Controller Interrupt Mask Register |
| 0x20 | SDRC_ISR | SDRAM Controller Interrupt Mask Register |
| Offset | Name | Description | ||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 3..0 | SDRC_MODE AT91C_SDRC_MODE | Mode 0: Normal Mode. 1: Issue a NOP Command at every access. 2: Issue a All Banks Precharge Command at every access. 3: Issue a Load Mode Register at every access. 4: Issue a Refresh
| ||||||||||||||||||
| 4 | SDRC_DBW AT91C_SDRC_DBW | Data Bus Width 0: 32 bits. 1: 16bits.
|
| Offset | Name | Description |
|---|---|---|
| 11..0 | SDRC_COUNT AT91C_SDRC_COUNT | Refresh Counter |
| Offset | Name | Description | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 1..0 | SDRC_NC AT91C_SDRC_NC | Number of Column Bits 0: 8. 1: 9. 3: 10. 3: 11.
| |||||||||||||||
| 3..2 | SDRC_NR AT91C_SDRC_NR | Number of Row Bits 0: 11. 1: 12. 3: 13. 3: Reserved.
| |||||||||||||||
| 4 | SDRC_NB AT91C_SDRC_NB | Number of Banks 0: 2. 1: 4.
| |||||||||||||||
| 6..5 | SDRC_CAS AT91C_SDRC_CAS | CAS Latency 0: Reserved. 1: Reserved. 2: 2. 3: Reserved.
| |||||||||||||||
| 10..7 | SDRC_TWR AT91C_SDRC_TWR | Number of Write Recovery Time Cycles | |||||||||||||||
| 14..11 | SDRC_TRC AT91C_SDRC_TRC | Number of RAS Cycle Time Cycles | |||||||||||||||
| 18..15 | SDRC_TRP AT91C_SDRC_TRP | Number of RAS Precharge Time Cycles | |||||||||||||||
| 22..19 | SDRC_TRCD AT91C_SDRC_TRCD | Number of RAS to CAS Delay Cycles | |||||||||||||||
| 26..23 | SDRC_TRAS AT91C_SDRC_TRAS | Number of RAS Active Time Cycles | |||||||||||||||
| 30..27 | SDRC_TXSR AT91C_SDRC_TXSR | Number of Command Recovery Time Cycles |
| Offset | Name | Description |
|---|---|---|
| 0 | SDRC_SRCB AT91C_SDRC_SRCB | Self-refresh Command Bit |
| Offset | Name | Description |
|---|---|---|
| 0 | SDRC_LPCB AT91C_SDRC_LPCB | Low-power Command Bit |
| Offset | Name | Description |
|---|---|---|
| 0 | SDRC_RES AT91C_SDRC_RES | Refresh Error Status |
| Offset | Name | Description |
|---|---|---|
| 0 | SDRC_RES AT91C_SDRC_RES | Refresh Error Status |
| Offset | Name | Description |
|---|---|---|
| 0 | SDRC_RES AT91C_SDRC_RES | Refresh Error Status |
| Offset | Name | Description |
|---|---|---|
| 0 | SDRC_RES AT91C_SDRC_RES | Refresh Error Status |