# AT91SAM7L128 TC0

## Timer Counter (TC0) User Interface

### Registers

Register Mapping
Address | Register | Name | Access | Reset
--- | --- | --- | --- | ---
0xFFFA0000 | Channel Control Register (channel = 0) | TC0_CCR0 | write-only | -
0xFFFA0004 | Channel Mode Register (channel = 0) | TC0_CMR0 | read-write | -
0xFFFA0010 | Counter Value (channel = 0) | TC0_CV0 | read-only | -
0xFFFA0014 | Register A (channel = 0) | TC0_RA0 | read-write | -
0xFFFA0018 | Register B (channel = 0) | TC0_RB0 | read-write | -
0xFFFA001C | Register C (channel = 0) | TC0_RC0 | read-write | -
0xFFFA0020 | Status Register (channel = 0) | TC0_SR0 | read-only | -
0xFFFA0024 | Interrupt Enable Register (channel = 0) | TC0_IER0 | write-only | -
0xFFFA0028 | Interrupt Disable Register (channel = 0) | TC0_IDR0 | write-only | -
0xFFFA002C | Interrupt Mask Register (channel = 0) | TC0_IMR0 | read-only | -
0xFFFA0040 | Channel Control Register (channel = 1) | TC0_CCR1 | write-only | -
0xFFFA0044 | Channel Mode Register (channel = 1) | TC0_CMR1 | read-write | -
0xFFFA0050 | Counter Value (channel = 1) | TC0_CV1 | read-only | -
0xFFFA0054 | Register A (channel = 1) | TC0_RA1 | read-write | -
0xFFFA0058 | Register B (channel = 1) | TC0_RB1 | read-write | -
0xFFFA005C | Register C (channel = 1) | TC0_RC1 | read-write | -
0xFFFA0060 | Status Register (channel = 1) | TC0_SR1 | read-only | -
0xFFFA0064 | Interrupt Enable Register (channel = 1) | TC0_IER1 | write-only | -
0xFFFA0068 | Interrupt Disable Register (channel = 1) | TC0_IDR1 | write-only | -
0xFFFA006C | Interrupt Mask Register (channel = 1) | TC0_IMR1 | read-only | -
0xFFFA0080 | Channel Control Register (channel = 2) | TC0_CCR2 | write-only | -
0xFFFA0084 | Channel Mode Register (channel = 2) | TC0_CMR2 | read-write | -
0xFFFA0090 | Counter Value (channel = 2) | TC0_CV2 | read-only | -
0xFFFA0094 | Register A (channel = 2) | TC0_RA2 | read-write | -
0xFFFA0098 | Register B (channel = 2) | TC0_RB2 | read-write | -
0xFFFA009C | Register C (channel = 2) | TC0_RC2 | read-write | -
0xFFFA00A0 | Status Register (channel = 2) | TC0_SR2 | read-only | -
0xFFFA00A4 | Interrupt Enable Register (channel = 2) | TC0_IER2 | write-only | -
0xFFFA00A8 | Interrupt Disable Register (channel = 2) | TC0_IDR2 | write-only | -
0xFFFA00AC | Interrupt Mask Register (channel = 2) | TC0_IMR2 | read-only | -
0xFFFA00C0 | Block Control Register | TC0_BCR | write-only | -
0xFFFA00C4 | Block Mode Register | TC0_BMR | read-write | -
0xFFFA00FC | Version Register | TC0_VER | read-only | -

### Register Fields

#### TC0 Channel Control Register (channel = 0)

Name: TC0_CCR0

Access: write-only

Address: 0xFFFA0000

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | SWTRG | CLKDIS | CLKEN

- CLKEN: Counter Clock Enable Command

- 0 = No effect.
- 1 = Enables the clock if CLKDIS is not 1.

- CLKDIS: Counter Clock Disable Command

- 0 = No effect.
- 1 = Disables the clock.

- SWTRG: Software Trigger Command

- 0 = No effect.
- 1 = A software trigger is performed: the counter is reset and the clock is started.

#### TC0 Channel Mode Register (channel = 0)

Name: TC0_CMR0

Access: read-write

Address: 0xFFFA0004

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | LDRB | LDRA
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
WAVE | CPCTRG | - | - | - | ABETRG | ETRGEDG
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
LDBDIS | LDBSTOP | BURST | CLKI | TCCLKS

- TCCLKS: Clock Selection

- 0x0 = TIMER_CLOCK1
- 0x1 = TIMER_CLOCK2
- 0x2 = TIMER_CLOCK3
- 0x3 = TIMER_CLOCK4
- 0x4 = TIMER_CLOCK5
- 0x5 = XC0
- 0x6 = XC1
- 0x7 = XC2

- CLKI: Clock Invert

- 0 = Counter is incremented on rising edge of the clock.
- 1 = Counter is incremented on falling edge of the clock.

- BURST: Burst Signal Selection

- 0x0 = The clock is not gated by an external signal.
- 0x1 = XC0 is ANDed with the selected clock.
- 0x2 = XC1 is ANDed with the selected clock.
- 0x3 = XC2 is ANDed with the selected clock.

- LDBSTOP: Counter Clock Stopped with RB Loading

- 0 = Counter clock is not stopped when RB loading occurs.
- 1 = Counter clock is stopped when RB loading occurs.

- LDBDIS: Counter Clock Disable with RB Loading

- 0 = Counter clock is not disabled when RB loading occurs.
- 1 = Counter clock is disabled when RB loading occurs.

- ETRGEDG: External Trigger Edge Selection

- 0x0 = none
- 0x1 = rising edge
- 0x2 = falling edge
- 0x3 = each edge

- ABETRG: TIOA or TIOB External Trigger Selection

- 0 = TIOB is used as an external trigger.
- 1 = TIOA is used as an external trigger.

- CPCTRG: RC Compare Trigger Enable

- 0 = RC Compare has no effect on the counter and its clock.
- 1 = RC Compare resets the counter and starts the counter clock.

- WAVE

- 0 = Capture Mode is enabled.
- 1 = Capture Mode is disabled (Waveform Mode is enabled).

- LDRA: RA Loading Selection

- 0x0 = none
- 0x1 = rising edge of TIOA
- 0x2 = falling edge of TIOA
- 0x3 = each edge of TIOA

- LDRB: RB Loading Selection

- 0x0 = none
- 0x1 = rising edge of TIOA
- 0x2 = falling edge of TIOA
- 0x3 = each edge of TIOA

#### TC0 Counter Value (channel = 0)

Name: TC0_CV0

Access: read-only

Address: 0xFFFA0010

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
CV
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CV

- CV: Counter Value

-

#### TC0 Register A (channel = 0)

Name: TC0_RA0

Access: read-write

Address: 0xFFFA0014

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RA
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RA

- RA: Register A

-

#### TC0 Register B (channel = 0)

Name: TC0_RB0

Access: read-write

Address: 0xFFFA0018

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RB
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RB

- RB: Register B

-

#### TC0 Register C (channel = 0)

Name: TC0_RC0

Access: read-write

Address: 0xFFFA001C

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RC
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RC

- RC: Register C

-

#### TC0 Status Register (channel = 0)

Name: TC0_SR0

Access: read-only

Address: 0xFFFA0020

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | MTIOB | MTIOA | CLKSTA
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
ETRGS | LDRBS | LDRAS | CPCS | CPBS | CPAS | LOVRS | COVFS

- COVFS: Counter Overflow Status

- 0 = No counter overflow has occurred since the last read of the Status Register.
- 1 = A counter overflow has occurred since the last read of the Status Register.

- LOVRS: Load Overrun Status

- 0 = Load overrun has not occurred since the last read of the Status Register or WAVE = 1.
- 1 = RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the Sta- tus Register, if WAVE = 0.

- CPAS: RA Compare Status

- 0 = RA Compare has not occurred since the last read of the Status Register or WAVE = 0.
- 1 = RA Compare has occurred since the last read of the Status Register, if WAVE = 1.

- CPBS: RB Compare Status

- 0 = RB Compare has not occurred since the last read of the Status Register or WAVE = 0.
- 1 = RB Compare has occurred since the last read of the Status Register, if WAVE = 1.

- CPCS: RC Compare Status

- 0 = RC Compare has not occurred since the last read of the Status Register.
- 1 = RC Compare has occurred since the last read of the Status Register.

- LDRAS: RA Loading Status

- 0 = RA Load has not occurred since the last read of the Status Register or WAVE = 1.
- 1 = RA Load has occurred since the last read of the Status Register, if WAVE = 0.

- LDRBS: RB Loading Status

- 0 = RB Load has not occurred since the last read of the Status Register or WAVE = 1.
- 1 = RB Load has occurred since the last read of the Status Register, if WAVE = 0.

- ETRGS: External Trigger Status

- 0 = External trigger has not occurred since the last read of the Status Register.
- 1 = External trigger has occurred since the last read of the Status Register.

- CLKSTA: Clock Enabling Status

- 0 = Clock is disabled.
- 1 = Clock is enabled.

- MTIOA: TIOA Mirror

- 0 = TIOA is low. If WAVE = 0, this means that TIOA pin is low. If WAVE = 1, this means that TIOA is driven low.
- 1 = TIOA is high. If WAVE = 0, this means that TIOA pin is high. If WAVE = 1, this means that TIOA is driven high.

- MTIOB: TIOB Mirror

- 0 = TIOB is low. If WAVE = 0, this means that TIOB pin is low. If WAVE = 1, this means that TIOB is driven low.
- 1 = TIOB is high. If WAVE = 0, this means that TIOB pin is high. If WAVE = 1, this means that TIOB is driven high.

#### TC0 Interrupt Enable Register (channel = 0)

Name: TC0_IER0

Access: write-only

Address: 0xFFFA0024

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
ETRGS | LDRBS | LDRAS | CPCS | CPBS | CPAS | LOVRS | COVFS

- COVFS: Counter Overflow

- 0 = No effect.
- 1 = Enables the Counter Overflow Interrupt.

- LOVRS: Load Overrun

- 0 = No effect.
- 1 = Enables the Load Overrun Interrupt.

- CPAS: RA Compare

- 0 = No effect.
- 1 = Enables the RA Compare Interrupt.

- CPBS: RB Compare

- 0 = No effect.
- 1 = Enables the RB Compare Interrupt.

- CPCS: RC Compare

- 0 = No effect.
- 1 = Enables the RC Compare Interrupt.

- LDRAS: RA Loading

- 0 = No effect.
- 1 = Enables the RA Load Interrupt.

- LDRBS: RB Loading

- 0 = No effect.
- 1 = Enables the RB Load Interrupt.

- ETRGS: External Trigger

- 0 = No effect.
- 1 = Enables the External Trigger Interrupt.

#### TC0 Interrupt Disable Register (channel = 0)

Name: TC0_IDR0

Access: write-only

Address: 0xFFFA0028

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
ETRGS | LDRBS | LDRAS | CPCS | CPBS | CPAS | LOVRS | COVFS

- COVFS: Counter Overflow

- 0 = No effect.
- 1 = Disables the Counter Overflow Interrupt.

- LOVRS: Load Overrun

- 0 = No effect.
- 1 = Disables the Load Overrun Interrupt (if WAVE = 0).

- CPAS: RA Compare

- 0 = No effect.
- 1 = Disables the RA Compare Interrupt (if WAVE = 1).

- CPBS: RB Compare

- 0 = No effect.
- 1 = Disables the RB Compare Interrupt (if WAVE = 1).

- CPCS: RC Compare

- 0 = No effect.
- 1 = Disables the RC Compare Interrupt.

- LDRAS: RA Loading

- 0 = No effect.
- 1 = Disables the RA Load Interrupt (if WAVE = 0).

- LDRBS: RB Loading

- 0 = No effect.
- 1 = Disables the RB Load Interrupt (if WAVE = 0).

- ETRGS: External Trigger

- 0 = No effect.
- 1 = Disables the External Trigger Interrupt.

#### TC0 Interrupt Mask Register (channel = 0)

Name: TC0_IMR0

Access: read-only

Address: 0xFFFA002C

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
ETRGS | LDRBS | LDRAS | CPCS | CPBS | CPAS | LOVRS | COVFS

- COVFS: Counter Overflow

- 0 = The Counter Overflow Interrupt is disabled.
- 1 = The Counter Overflow Interrupt is enabled.

- LOVRS: Load Overrun

- 0 = The Load Overrun Interrupt is disabled.
- 1 = The Load Overrun Interrupt is enabled.

- CPAS: RA Compare

- 0 = The RA Compare Interrupt is disabled.
- 1 = The RA Compare Interrupt is enabled.

- CPBS: RB Compare

- 0 = The RB Compare Interrupt is disabled.
- 1 = The RB Compare Interrupt is enabled.

- CPCS: RC Compare

- 0 = The RC Compare Interrupt is disabled.
- 1 = The RC Compare Interrupt is enabled.

- LDRAS: RA Loading

- 0 = The Load RA Interrupt is disabled.
- 1 = The Load RA Interrupt is enabled.

- LDRBS: RB Loading

- 0 = The Load RB Interrupt is disabled.
- 1 = The Load RB Interrupt is enabled.

- ETRGS: External Trigger

- 0 = The External Trigger Interrupt is disabled.
- 1 = The External Trigger Interrupt is enabled.

#### TC0 Channel Control Register (channel = 1)

Name: TC0_CCR1

Access: write-only

Address: 0xFFFA0040

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | SWTRG | CLKDIS | CLKEN

- CLKEN: Counter Clock Enable Command

- 0 = No effect.
- 1 = Enables the clock if CLKDIS is not 1.

- CLKDIS: Counter Clock Disable Command

- 0 = No effect.
- 1 = Disables the clock.

- SWTRG: Software Trigger Command

- 0 = No effect.
- 1 = A software trigger is performed: the counter is reset and the clock is started.

#### TC0 Channel Mode Register (channel = 1)

Name: TC0_CMR1

Access: read-write

Address: 0xFFFA0044

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | LDRB | LDRA
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
WAVE | CPCTRG | - | - | - | ABETRG | ETRGEDG
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
LDBDIS | LDBSTOP | BURST | CLKI | TCCLKS

- TCCLKS: Clock Selection

- 0x0 = TIMER_CLOCK1
- 0x1 = TIMER_CLOCK2
- 0x2 = TIMER_CLOCK3
- 0x3 = TIMER_CLOCK4
- 0x4 = TIMER_CLOCK5
- 0x5 = XC0
- 0x6 = XC1
- 0x7 = XC2

- CLKI: Clock Invert

- 0 = Counter is incremented on rising edge of the clock.
- 1 = Counter is incremented on falling edge of the clock.

- BURST: Burst Signal Selection

- 0x0 = The clock is not gated by an external signal.
- 0x1 = XC0 is ANDed with the selected clock.
- 0x2 = XC1 is ANDed with the selected clock.
- 0x3 = XC2 is ANDed with the selected clock.

- LDBSTOP: Counter Clock Stopped with RB Loading

- 0 = Counter clock is not stopped when RB loading occurs.
- 1 = Counter clock is stopped when RB loading occurs.

- LDBDIS: Counter Clock Disable with RB Loading

- 0 = Counter clock is not disabled when RB loading occurs.
- 1 = Counter clock is disabled when RB loading occurs.

- ETRGEDG: External Trigger Edge Selection

- 0x0 = none
- 0x1 = rising edge
- 0x2 = falling edge
- 0x3 = each edge

- ABETRG: TIOA or TIOB External Trigger Selection

- 0 = TIOB is used as an external trigger.
- 1 = TIOA is used as an external trigger.

- CPCTRG: RC Compare Trigger Enable

- 0 = RC Compare has no effect on the counter and its clock.
- 1 = RC Compare resets the counter and starts the counter clock.

- WAVE

- 0 = Capture Mode is enabled.
- 1 = Capture Mode is disabled (Waveform Mode is enabled).

- LDRA: RA Loading Selection

- 0x0 = none
- 0x1 = rising edge of TIOA
- 0x2 = falling edge of TIOA
- 0x3 = each edge of TIOA

- LDRB: RB Loading Selection

- 0x0 = none
- 0x1 = rising edge of TIOA
- 0x2 = falling edge of TIOA
- 0x3 = each edge of TIOA

#### TC0 Counter Value (channel = 1)

Name: TC0_CV1

Access: read-only

Address: 0xFFFA0050

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
CV
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CV

- CV: Counter Value

-

#### TC0 Register A (channel = 1)

Name: TC0_RA1

Access: read-write

Address: 0xFFFA0054

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RA
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RA

- RA: Register A

-

#### TC0 Register B (channel = 1)

Name: TC0_RB1

Access: read-write

Address: 0xFFFA0058

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RB
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RB

- RB: Register B

-

#### TC0 Register C (channel = 1)

Name: TC0_RC1

Access: read-write

Address: 0xFFFA005C

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RC
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RC

- RC: Register C

-

#### TC0 Status Register (channel = 1)

Name: TC0_SR1

Access: read-only

Address: 0xFFFA0060

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | MTIOB | MTIOA | CLKSTA
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
ETRGS | LDRBS | LDRAS | CPCS | CPBS | CPAS | LOVRS | COVFS

- COVFS: Counter Overflow Status

- 0 = No counter overflow has occurred since the last read of the Status Register.
- 1 = A counter overflow has occurred since the last read of the Status Register.

- LOVRS: Load Overrun Status

- 0 = Load overrun has not occurred since the last read of the Status Register or WAVE = 1.
- 1 = RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the Sta- tus Register, if WAVE = 0.

- CPAS: RA Compare Status

- 0 = RA Compare has not occurred since the last read of the Status Register or WAVE = 0.
- 1 = RA Compare has occurred since the last read of the Status Register, if WAVE = 1.

- CPBS: RB Compare Status

- 0 = RB Compare has not occurred since the last read of the Status Register or WAVE = 0.
- 1 = RB Compare has occurred since the last read of the Status Register, if WAVE = 1.

- CPCS: RC Compare Status

- 0 = RC Compare has not occurred since the last read of the Status Register.
- 1 = RC Compare has occurred since the last read of the Status Register.

- LDRAS: RA Loading Status

- 0 = RA Load has not occurred since the last read of the Status Register or WAVE = 1.
- 1 = RA Load has occurred since the last read of the Status Register, if WAVE = 0.

- LDRBS: RB Loading Status

- 0 = RB Load has not occurred since the last read of the Status Register or WAVE = 1.
- 1 = RB Load has occurred since the last read of the Status Register, if WAVE = 0.

- ETRGS: External Trigger Status

- 0 = External trigger has not occurred since the last read of the Status Register.
- 1 = External trigger has occurred since the last read of the Status Register.

- CLKSTA: Clock Enabling Status

- 0 = Clock is disabled.
- 1 = Clock is enabled.

- MTIOA: TIOA Mirror

- 0 = TIOA is low. If WAVE = 0, this means that TIOA pin is low. If WAVE = 1, this means that TIOA is driven low.
- 1 = TIOA is high. If WAVE = 0, this means that TIOA pin is high. If WAVE = 1, this means that TIOA is driven high.

- MTIOB: TIOB Mirror

- 0 = TIOB is low. If WAVE = 0, this means that TIOB pin is low. If WAVE = 1, this means that TIOB is driven low.
- 1 = TIOB is high. If WAVE = 0, this means that TIOB pin is high. If WAVE = 1, this means that TIOB is driven high.

#### TC0 Interrupt Enable Register (channel = 1)

Name: TC0_IER1

Access: write-only

Address: 0xFFFA0064

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
ETRGS | LDRBS | LDRAS | CPCS | CPBS | CPAS | LOVRS | COVFS

- COVFS: Counter Overflow

- 0 = No effect.
- 1 = Enables the Counter Overflow Interrupt.

- LOVRS: Load Overrun

- 0 = No effect.
- 1 = Enables the Load Overrun Interrupt.

- CPAS: RA Compare

- 0 = No effect.
- 1 = Enables the RA Compare Interrupt.

- CPBS: RB Compare

- 0 = No effect.
- 1 = Enables the RB Compare Interrupt.

- CPCS: RC Compare

- 0 = No effect.
- 1 = Enables the RC Compare Interrupt.

- LDRAS: RA Loading

- 0 = No effect.
- 1 = Enables the RA Load Interrupt.

- LDRBS: RB Loading

- 0 = No effect.
- 1 = Enables the RB Load Interrupt.

- ETRGS: External Trigger

- 0 = No effect.
- 1 = Enables the External Trigger Interrupt.

#### TC0 Interrupt Disable Register (channel = 1)

Name: TC0_IDR1

Access: write-only

Address: 0xFFFA0068

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
ETRGS | LDRBS | LDRAS | CPCS | CPBS | CPAS | LOVRS | COVFS

- COVFS: Counter Overflow

- 0 = No effect.
- 1 = Disables the Counter Overflow Interrupt.

- LOVRS: Load Overrun

- 0 = No effect.
- 1 = Disables the Load Overrun Interrupt (if WAVE = 0).

- CPAS: RA Compare

- 0 = No effect.
- 1 = Disables the RA Compare Interrupt (if WAVE = 1).

- CPBS: RB Compare

- 0 = No effect.
- 1 = Disables the RB Compare Interrupt (if WAVE = 1).

- CPCS: RC Compare

- 0 = No effect.
- 1 = Disables the RC Compare Interrupt.

- LDRAS: RA Loading

- 0 = No effect.
- 1 = Disables the RA Load Interrupt (if WAVE = 0).

- LDRBS: RB Loading

- 0 = No effect.
- 1 = Disables the RB Load Interrupt (if WAVE = 0).

- ETRGS: External Trigger

- 0 = No effect.
- 1 = Disables the External Trigger Interrupt.

#### TC0 Interrupt Mask Register (channel = 1)

Name: TC0_IMR1

Access: read-only

Address: 0xFFFA006C

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
ETRGS | LDRBS | LDRAS | CPCS | CPBS | CPAS | LOVRS | COVFS

- COVFS: Counter Overflow

- 0 = The Counter Overflow Interrupt is disabled.
- 1 = The Counter Overflow Interrupt is enabled.

- LOVRS: Load Overrun

- 0 = The Load Overrun Interrupt is disabled.
- 1 = The Load Overrun Interrupt is enabled.

- CPAS: RA Compare

- 0 = The RA Compare Interrupt is disabled.
- 1 = The RA Compare Interrupt is enabled.

- CPBS: RB Compare

- 0 = The RB Compare Interrupt is disabled.
- 1 = The RB Compare Interrupt is enabled.

- CPCS: RC Compare

- 0 = The RC Compare Interrupt is disabled.
- 1 = The RC Compare Interrupt is enabled.

- LDRAS: RA Loading

- 0 = The Load RA Interrupt is disabled.
- 1 = The Load RA Interrupt is enabled.

- LDRBS: RB Loading

- 0 = The Load RB Interrupt is disabled.
- 1 = The Load RB Interrupt is enabled.

- ETRGS: External Trigger

- 0 = The External Trigger Interrupt is disabled.
- 1 = The External Trigger Interrupt is enabled.

#### TC0 Channel Control Register (channel = 2)

Name: TC0_CCR2

Access: write-only

Address: 0xFFFA0080

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | SWTRG | CLKDIS | CLKEN

- CLKEN: Counter Clock Enable Command

- 0 = No effect.
- 1 = Enables the clock if CLKDIS is not 1.

- CLKDIS: Counter Clock Disable Command

- 0 = No effect.
- 1 = Disables the clock.

- SWTRG: Software Trigger Command

- 0 = No effect.
- 1 = A software trigger is performed: the counter is reset and the clock is started.

#### TC0 Channel Mode Register (channel = 2)

Name: TC0_CMR2

Access: read-write

Address: 0xFFFA0084

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | LDRB | LDRA
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
WAVE | CPCTRG | - | - | - | ABETRG | ETRGEDG
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
LDBDIS | LDBSTOP | BURST | CLKI | TCCLKS

- TCCLKS: Clock Selection

- 0x0 = TIMER_CLOCK1
- 0x1 = TIMER_CLOCK2
- 0x2 = TIMER_CLOCK3
- 0x3 = TIMER_CLOCK4
- 0x4 = TIMER_CLOCK5
- 0x5 = XC0
- 0x6 = XC1
- 0x7 = XC2

- CLKI: Clock Invert

- 0 = Counter is incremented on rising edge of the clock.
- 1 = Counter is incremented on falling edge of the clock.

- BURST: Burst Signal Selection

- 0x0 = The clock is not gated by an external signal.
- 0x1 = XC0 is ANDed with the selected clock.
- 0x2 = XC1 is ANDed with the selected clock.
- 0x3 = XC2 is ANDed with the selected clock.

- LDBSTOP: Counter Clock Stopped with RB Loading

- 0 = Counter clock is not stopped when RB loading occurs.
- 1 = Counter clock is stopped when RB loading occurs.

- LDBDIS: Counter Clock Disable with RB Loading

- 0 = Counter clock is not disabled when RB loading occurs.
- 1 = Counter clock is disabled when RB loading occurs.

- ETRGEDG: External Trigger Edge Selection

- 0x0 = none
- 0x1 = rising edge
- 0x2 = falling edge
- 0x3 = each edge

- ABETRG: TIOA or TIOB External Trigger Selection

- 0 = TIOB is used as an external trigger.
- 1 = TIOA is used as an external trigger.

- CPCTRG: RC Compare Trigger Enable

- 0 = RC Compare has no effect on the counter and its clock.
- 1 = RC Compare resets the counter and starts the counter clock.

- WAVE

- 0 = Capture Mode is enabled.
- 1 = Capture Mode is disabled (Waveform Mode is enabled).

- LDRA: RA Loading Selection

- 0x0 = none
- 0x1 = rising edge of TIOA
- 0x2 = falling edge of TIOA
- 0x3 = each edge of TIOA

- LDRB: RB Loading Selection

- 0x0 = none
- 0x1 = rising edge of TIOA
- 0x2 = falling edge of TIOA
- 0x3 = each edge of TIOA

#### TC0 Counter Value (channel = 2)

Name: TC0_CV2

Access: read-only

Address: 0xFFFA0090

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
CV
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CV

- CV: Counter Value

-

#### TC0 Register A (channel = 2)

Name: TC0_RA2

Access: read-write

Address: 0xFFFA0094

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RA
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RA

- RA: Register A

-

#### TC0 Register B (channel = 2)

Name: TC0_RB2

Access: read-write

Address: 0xFFFA0098

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RB
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RB

- RB: Register B

-

#### TC0 Register C (channel = 2)

Name: TC0_RC2

Access: read-write

Address: 0xFFFA009C

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RC
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RC

- RC: Register C

-

#### TC0 Status Register (channel = 2)

Name: TC0_SR2

Access: read-only

Address: 0xFFFA00A0

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | MTIOB | MTIOA | CLKSTA
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
ETRGS | LDRBS | LDRAS | CPCS | CPBS | CPAS | LOVRS | COVFS

- COVFS: Counter Overflow Status

- 0 = No counter overflow has occurred since the last read of the Status Register.
- 1 = A counter overflow has occurred since the last read of the Status Register.

- LOVRS: Load Overrun Status

- 0 = Load overrun has not occurred since the last read of the Status Register or WAVE = 1.
- 1 = RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the Sta- tus Register, if WAVE = 0.

- CPAS: RA Compare Status

- 0 = RA Compare has not occurred since the last read of the Status Register or WAVE = 0.
- 1 = RA Compare has occurred since the last read of the Status Register, if WAVE = 1.

- CPBS: RB Compare Status

- 0 = RB Compare has not occurred since the last read of the Status Register or WAVE = 0.
- 1 = RB Compare has occurred since the last read of the Status Register, if WAVE = 1.

- CPCS: RC Compare Status

- 0 = RC Compare has not occurred since the last read of the Status Register.
- 1 = RC Compare has occurred since the last read of the Status Register.

- LDRAS: RA Loading Status

- 0 = RA Load has not occurred since the last read of the Status Register or WAVE = 1.
- 1 = RA Load has occurred since the last read of the Status Register, if WAVE = 0.

- LDRBS: RB Loading Status

- 0 = RB Load has not occurred since the last read of the Status Register or WAVE = 1.
- 1 = RB Load has occurred since the last read of the Status Register, if WAVE = 0.

- ETRGS: External Trigger Status

- 0 = External trigger has not occurred since the last read of the Status Register.
- 1 = External trigger has occurred since the last read of the Status Register.

- CLKSTA: Clock Enabling Status

- 0 = Clock is disabled.
- 1 = Clock is enabled.

- MTIOA: TIOA Mirror

- 0 = TIOA is low. If WAVE = 0, this means that TIOA pin is low. If WAVE = 1, this means that TIOA is driven low.
- 1 = TIOA is high. If WAVE = 0, this means that TIOA pin is high. If WAVE = 1, this means that TIOA is driven high.

- MTIOB: TIOB Mirror

- 0 = TIOB is low. If WAVE = 0, this means that TIOB pin is low. If WAVE = 1, this means that TIOB is driven low.
- 1 = TIOB is high. If WAVE = 0, this means that TIOB pin is high. If WAVE = 1, this means that TIOB is driven high.

#### TC0 Interrupt Enable Register (channel = 2)

Name: TC0_IER2

Access: write-only

Address: 0xFFFA00A4

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
ETRGS | LDRBS | LDRAS | CPCS | CPBS | CPAS | LOVRS | COVFS

- COVFS: Counter Overflow

- 0 = No effect.
- 1 = Enables the Counter Overflow Interrupt.

- LOVRS: Load Overrun

- 0 = No effect.
- 1 = Enables the Load Overrun Interrupt.

- CPAS: RA Compare

- 0 = No effect.
- 1 = Enables the RA Compare Interrupt.

- CPBS: RB Compare

- 0 = No effect.
- 1 = Enables the RB Compare Interrupt.

- CPCS: RC Compare

- 0 = No effect.
- 1 = Enables the RC Compare Interrupt.

- LDRAS: RA Loading

- 0 = No effect.
- 1 = Enables the RA Load Interrupt.

- LDRBS: RB Loading

- 0 = No effect.
- 1 = Enables the RB Load Interrupt.

- ETRGS: External Trigger

- 0 = No effect.
- 1 = Enables the External Trigger Interrupt.

#### TC0 Interrupt Disable Register (channel = 2)

Name: TC0_IDR2

Access: write-only

Address: 0xFFFA00A8

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
ETRGS | LDRBS | LDRAS | CPCS | CPBS | CPAS | LOVRS | COVFS

- COVFS: Counter Overflow

- 0 = No effect.
- 1 = Disables the Counter Overflow Interrupt.

- LOVRS: Load Overrun

- 0 = No effect.
- 1 = Disables the Load Overrun Interrupt (if WAVE = 0).

- CPAS: RA Compare

- 0 = No effect.
- 1 = Disables the RA Compare Interrupt (if WAVE = 1).

- CPBS: RB Compare

- 0 = No effect.
- 1 = Disables the RB Compare Interrupt (if WAVE = 1).

- CPCS: RC Compare

- 0 = No effect.
- 1 = Disables the RC Compare Interrupt.

- LDRAS: RA Loading

- 0 = No effect.
- 1 = Disables the RA Load Interrupt (if WAVE = 0).

- LDRBS: RB Loading

- 0 = No effect.
- 1 = Disables the RB Load Interrupt (if WAVE = 0).

- ETRGS: External Trigger

- 0 = No effect.
- 1 = Disables the External Trigger Interrupt.

#### TC0 Interrupt Mask Register (channel = 2)

Name: TC0_IMR2

Access: read-only

Address: 0xFFFA00AC

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
ETRGS | LDRBS | LDRAS | CPCS | CPBS | CPAS | LOVRS | COVFS

- COVFS: Counter Overflow

- 0 = The Counter Overflow Interrupt is disabled.
- 1 = The Counter Overflow Interrupt is enabled.

- LOVRS: Load Overrun

- 0 = The Load Overrun Interrupt is disabled.
- 1 = The Load Overrun Interrupt is enabled.

- CPAS: RA Compare

- 0 = The RA Compare Interrupt is disabled.
- 1 = The RA Compare Interrupt is enabled.

- CPBS: RB Compare

- 0 = The RB Compare Interrupt is disabled.
- 1 = The RB Compare Interrupt is enabled.

- CPCS: RC Compare

- 0 = The RC Compare Interrupt is disabled.
- 1 = The RC Compare Interrupt is enabled.

- LDRAS: RA Loading

- 0 = The Load RA Interrupt is disabled.
- 1 = The Load RA Interrupt is enabled.

- LDRBS: RB Loading

- 0 = The Load RB Interrupt is disabled.
- 1 = The Load RB Interrupt is enabled.

- ETRGS: External Trigger

- 0 = The External Trigger Interrupt is disabled.
- 1 = The External Trigger Interrupt is enabled.

#### TC0 Block Control Register

Name: TC0_BCR

Access: write-only

Address: 0xFFFA00C0

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | - | SYNC

- SYNC: Synchro Command

- 0 = No effect.
- 1 = Asserts the SYNC signal which generates a software trigger simultaneously for each of the channels.

#### TC0 Block Mode Register

Name: TC0_BMR

Access: read-write

Address: 0xFFFA00C4

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | TC2XC2S | TC1XC1S | TC0XC0S

- TC0XC0S: External Clock Signal 0 Selection

- 0x0 = TCLK0
- 0x1 = none
- 0x2 = TIOA1
- 0x3 = TIOA2

- TC1XC1S: External Clock Signal 1 Selection

- 0x0 = TCLK1
- 0x1 = none
- 0x2 = TIOA0
- 0x3 = TIOA2

- TC2XC2S: External Clock Signal 2 Selection

- 0x0 = TCLK2
- 0x1 = none
- 0x2 = TIOA0
- 0x3 = TIOA1

#### TC0 Version Register

Name: TC0_VER

Access: read-only

Address: 0xFFFA00FC

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | MFN
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | VERSION
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
VERSION

- VERSION

-

- MFN

-