# AT91SAM7L128 DBGU

## Debug Unit (DBGU) User Interface

### Registers

Register Mapping
Address | Register | Name | Access | Reset
--- | --- | --- | --- | ---
0xFFFFF200 | Control Register | DBGU_CR | write-only | -
0xFFFFF204 | Mode Register | DBGU_MR | read-write | 0x0
0xFFFFF208 | Interrupt Enable Register | DBGU_IER | write-only | -
0xFFFFF20C | Interrupt Disable Register | DBGU_IDR | write-only | -
0xFFFFF210 | Interrupt Mask Register | DBGU_IMR | read-only | 0x0
0xFFFFF214 | Status Register | DBGU_SR | read-only | -
0xFFFFF218 | Receive Holding Register | DBGU_RHR | read-only | 0x0
0xFFFFF21C | Transmit Holding Register | DBGU_THR | write-only | -
0xFFFFF220 | Baud Rate Generator Register | DBGU_BRGR | read-write | 0x0
0xFFFFF240 | Chip ID Register | DBGU_CIDR | read-only | -
0xFFFFF244 | Chip ID Extension Register | DBGU_EXID | read-only | -
0xFFFFF248 | Force NTRST Register | DBGU_FNR | read-write | 0x0
0xFFFFF300 | Receive Pointer Register | DBGU_RPR | read-write | 0x0
0xFFFFF304 | Receive Counter Register | DBGU_RCR | read-write | 0x0
0xFFFFF308 | Transmit Pointer Register | DBGU_TPR | read-write | 0x0
0xFFFFF30C | Transmit Counter Register | DBGU_TCR | read-write | 0x0
0xFFFFF310 | Receive Next Pointer Register | DBGU_RNPR | read-write | 0x0
0xFFFFF314 | Receive Next Counter Register | DBGU_RNCR | read-write | 0x0
0xFFFFF318 | Transmit Next Pointer Register | DBGU_TNPR | read-write | 0x0
0xFFFFF31C | Transmit Next Counter Register | DBGU_TNCR | read-write | 0x0
0xFFFFF320 | PDC Transfer Control Register | DBGU_PTCR | write-only | -
0xFFFFF324 | PDC Transfer Status Register | DBGU_PTSR | read-only | 0x0

### Register Fields

#### DBGU Control Register

Name: DBGU_CR

Access: write-only

Address: 0xFFFFF200

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | RSTSTA
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TXDIS | TXEN | RXDIS | RXEN | RSTTX | RSTRX | - | -

- RSTRX: Reset Receiver

- 0 = No effect.
- 1 = The receiver logic is reset and disabled. If a character is being received, the reception is aborted.

- RSTTX: Reset Transmitter

- 0 = No effect.
- 1 = The transmitter logic is reset and disabled. If a character is being transmitted, the transmission is aborted.

- RXEN: Receiver Enable

- 0 = No effect.
- 1 = The receiver is enabled if RXDIS is 0.

- RXDIS: Receiver Disable

- 0 = No effect.
- 1 = The receiver is disabled. If a character is being processed and RSTRX is not set, the character is completed before the receiver is stopped.

- TXEN: Transmitter Enable

- 0 = No effect.
- 1 = The transmitter is enabled if TXDIS is 0.

- TXDIS: Transmitter Disable

- 0 = No effect.
- 1 = The transmitter is disabled. If a character is being processed and a character has been written the DBGU_THR and RSTTX is not set, both characters are completed before the transmitter is stopped.

- RSTSTA: Reset Status Bits

- 0 = No effect.
- 1 = Resets the status bits PARE, FRAME and OVRE in the DBGU_SR.

#### DBGU Mode Register

Name: DBGU_MR

Access: read-write

Address: 0xFFFFF204

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
CHMODE | - | - | PAR | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | - | -

- PAR: Parity Type

-

- CHMODE: Channel Mode

- 0x0 = Normal Mode
- 0x1 = Automatic Echo
- 0x2 = Local Loopback
- 0x3 = Remote Loopback

#### DBGU Interrupt Enable Register

Name: DBGU_IER

Access: write-only

Address: 0xFFFFF208

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
COMMRX | COMMTX | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | RXBUFF | TXBUFE | - | TXEMPTY | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
PARE | FRAME | OVRE | ENDTX | ENDRX | - | TXRDY | RXRDY

- RXRDY: Enable RXRDY Interrupt

- 0 = No effect.
- 1 = Enables the corresponding interrupt.

- TXRDY: Enable TXRDY Interrupt

- 0 = No effect.
- 1 = Enables the corresponding interrupt.

- ENDRX: Enable End of Receive Transfer Interrupt

- 0 = No effect.
- 1 = Enables the corresponding interrupt.

- ENDTX: Enable End of Transmit Interrupt

- 0 = No effect.
- 1 = Enables the corresponding interrupt.

- OVRE: Enable Overrun Error Interrupt

- 0 = No effect.
- 1 = Enables the corresponding interrupt.

- FRAME: Enable Framing Error Interrupt

- 0 = No effect.
- 1 = Enables the corresponding interrupt.

- PARE: Enable Parity Error Interrupt

- 0 = No effect.
- 1 = Enables the corresponding interrupt.

- TXEMPTY: Enable TXEMPTY Interrupt

- 0 = No effect.
- 1 = Enables the corresponding interrupt.

- TXBUFE: Enable Buffer Empty Interrupt

- 0 = No effect.
- 1 = Enables the corresponding interrupt.

- RXBUFF: Enable Buffer Full Interrupt

- 0 = No effect.
- 1 = Enables the corresponding interrupt.

- COMMTX: Enable COMMTX (from ARM) Interrupt

- 0 = No effect.
- 1 = Enables the corresponding interrupt.

- COMMRX: Enable COMMRX (from ARM) Interrupt

- 0 = No effect.
- 1 = Enables the corresponding interrupt.

#### DBGU Interrupt Disable Register

Name: DBGU_IDR

Access: write-only

Address: 0xFFFFF20C

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
COMMRX | COMMTX | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | RXBUFF | TXBUFE | - | TXEMPTY | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
PARE | FRAME | OVRE | ENDTX | ENDRX | - | TXRDY | RXRDY

- RXRDY: Disable RXRDY Interrupt

- 0 = No effect.
- 1 = Disables the corresponding interrupt.

- TXRDY: Disable TXRDY Interrupt

- 0 = No effect.
- 1 = Disables the corresponding interrupt.

- ENDRX: Disable End of Receive Transfer Interrupt

- 0 = No effect.
- 1 = Disables the corresponding interrupt.

- ENDTX: Disable End of Transmit Interrupt

- 0 = No effect.
- 1 = Disables the corresponding interrupt.

- OVRE: Disable Overrun Error Interrupt

- 0 = No effect.
- 1 = Disables the corresponding interrupt.

- FRAME: Disable Framing Error Interrupt

- 0 = No effect.
- 1 = Disables the corresponding interrupt.

- PARE: Disable Parity Error Interrupt

- 0 = No effect.
- 1 = Disables the corresponding interrupt.

- TXEMPTY: Disable TXEMPTY Interrupt

- 0 = No effect.
- 1 = Disables the corresponding interrupt.

- TXBUFE: Disable Buffer Empty Interrupt

- 0 = No effect.
- 1 = Disables the corresponding interrupt.

- RXBUFF: Disable Buffer Full Interrupt

- 0 = No effect.
- 1 = Disables the corresponding interrupt.

- COMMTX: Disable COMMTX (from ARM) Interrupt

- 0 = No effect.
- 1 = Disables the corresponding interrupt.

- COMMRX: Disable COMMRX (from ARM) Interrupt

- 0 = No effect.
- 1 = Disables the corresponding interrupt.

#### DBGU Interrupt Mask Register

Name: DBGU_IMR

Access: read-only

Address: 0xFFFFF210

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
COMMRX | COMMTX | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | RXBUFF | TXBUFE | - | TXEMPTY | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
PARE | FRAME | OVRE | ENDTX | ENDRX | - | TXRDY | RXRDY

- RXRDY: Mask RXRDY Interrupt

- 0 = The corresponding interrupt is disabled.
- 1 = The corresponding interrupt is enabled.

- TXRDY: Disable TXRDY Interrupt

- 0 = The corresponding interrupt is disabled.
- 1 = The corresponding interrupt is enabled.

- ENDRX: Mask End of Receive Transfer Interrupt

- 0 = The corresponding interrupt is disabled.
- 1 = The corresponding interrupt is enabled.

- ENDTX: Mask End of Transmit Interrupt

- 0 = The corresponding interrupt is disabled.
- 1 = The corresponding interrupt is enabled.

- OVRE: Mask Overrun Error Interrupt

- 0 = The corresponding interrupt is disabled.
- 1 = The corresponding interrupt is enabled.

- FRAME: Mask Framing Error Interrupt

- 0 = The corresponding interrupt is disabled.
- 1 = The corresponding interrupt is enabled.

- PARE: Mask Parity Error Interrupt

- 0 = The corresponding interrupt is disabled.
- 1 = The corresponding interrupt is enabled.

- TXEMPTY: Mask TXEMPTY Interrupt

- 0 = The corresponding interrupt is disabled.
- 1 = The corresponding interrupt is enabled.

- TXBUFE: Mask TXBUFE Interrupt

- 0 = The corresponding interrupt is disabled.
- 1 = The corresponding interrupt is enabled.

- RXBUFF: Mask RXBUFF Interrupt

- 0 = The corresponding interrupt is disabled.
- 1 = The corresponding interrupt is enabled.

- COMMTX: Mask COMMTX Interrupt

- 0 = The corresponding interrupt is disabled.
- 1 = The corresponding interrupt is enabled.

- COMMRX: Mask COMMRX Interrupt

- 0 = The corresponding interrupt is disabled.
- 1 = The corresponding interrupt is enabled.

#### DBGU Status Register

Name: DBGU_SR

Access: read-only

Address: 0xFFFFF214

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
COMMRX | COMMTX | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | RXBUFF | TXBUFE | - | TXEMPTY | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
PARE | FRAME | OVRE | ENDTX | ENDRX | - | TXRDY | RXRDY

- RXRDY: Receiver Ready

- 0 = No character has been received since the last read of the DBGU_RHR or the receiver is disabled.
- 1 = At least one complete character has been received, transferred to DBGU_RHR and not yet read.

- TXRDY: Transmitter Ready

- 0 = A character has been written to DBGU_THR and not yet transferred to the Shift Register, or the transmitter is disabled.
- 1 = There is no character written to DBGU_THR not yet transferred to the Shift Register.

- ENDRX: End of Receiver Transfer

- 0 = The End of Transfer signal from the receiver Peripheral Data Controller channel is inactive.
- 1 = The End of Transfer signal from the receiver Peripheral Data Controller channel is active.

- ENDTX: End of Transmitter Transfer

- 0 = The End of Transfer signal from the transmitter Peripheral Data Controller channel is inactive.
- 1 = The End of Transfer signal from the transmitter Peripheral Data Controller channel is active.

- OVRE: Overrun Error

- 0 = No overrun error has occurred since the last RSTSTA.
- 1 = At least one overrun error has occurred since the last RSTSTA.

- FRAME: Framing Error

- 0 = No framing error has occurred since the last RSTSTA.
- 1 = At least one framing error has occurred since the last RSTSTA.

- PARE: Parity Error

- 0 = No parity error has occurred since the last RSTSTA.
- 1 = At least one parity error has occurred since the last RSTSTA.

- TXEMPTY: Transmitter Empty

- 0 = There are characters in DBGU_THR, or characters being processed by the transmitter, or the transmitter is disabled.
- 1 = There are no characters in DBGU_THR and there are no characters being processed by the transmitter.

- TXBUFE: Transmission Buffer Empty

- 0 = The buffer empty signal from the transmitter PDC channel is inactive.
- 1 = The buffer empty signal from the transmitter PDC channel is active.

- RXBUFF: Receive Buffer Full

- 0 = The buffer full signal from the receiver PDC channel is inactive.
- 1 = The buffer full signal from the receiver PDC channel is active.

- COMMTX: Debug Communication Channel Write Status

- 0 = COMMTX from the ARM processor is inactive.
- 1 = COMMTX from the ARM processor is active.

- COMMRX: Debug Communication Channel Read Status

- 0 = COMMRX from the ARM processor is inactive.
- 1 = COMMRX from the ARM processor is active.

#### DBGU Receive Holding Register

Name: DBGU_RHR

Access: read-only

Address: 0xFFFFF218

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RXCHR

- RXCHR: Received Character

-

#### DBGU Transmit Holding Register

Name: DBGU_THR

Access: write-only

Address: 0xFFFFF21C

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TXCHR

- TXCHR: Character to be Transmitted

-

#### DBGU Baud Rate Generator Register

Name: DBGU_BRGR

Access: read-write

Address: 0xFFFFF220

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
CD
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CD

- CD: Clock Divisor

-

#### DBGU Chip ID Register

Name: DBGU_CIDR

Access: read-only

Address: 0xFFFFF240

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
EXT | NVPTYP | ARCH
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
ARCH | SRAMSIZ
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
NVPSIZ2 | NVPSIZ
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
EPROC | VERSION

- VERSION: Version of the Device

-

- EPROC: Embedded Processor

- 0x1 = ARM946ES
- 0x2 = ARM7TDMI
- 0x4 = ARM920T
- 0x5 = ARM926EJS

- NVPSIZ: Nonvolatile Program Memory Size

- 0x0 = None
- 0x1 = 8K bytes
- 0x2 = 16K bytes
- 0x3 = 32K bytes
- 0x4 = Reserved
- 0x5 = 64K bytes
- 0x6 = Reserved
- 0x7 = 128K bytes
- 0x8 = Reserved
- 0x9 = 256K bytes
- 0xA = 512K bytes
- 0xB = Reserved
- 0xC = 1024K bytes
- 0xD = Reserved
- 0xE = 2048K bytes
- 0xF = Reserved

- NVPSIZ2

- 0x0 = None
- 0x1 = 8K bytes
- 0x2 = 16K bytes
- 0x3 = 32K bytes
- 0x4 = Reserved
- 0x5 = 64K bytes
- 0x6 = Reserved
- 0x7 = 128K bytes
- 0x8 = Reserved
- 0x9 = 256K bytes
- 0xA = 512K bytes
- 0xB = Reserved
- 0xC = 1024K bytes
- 0xD = Reserved
- 0xE = 2048K bytes
- 0xF = Reserved

- SRAMSIZ: Internal SRAM Size

- 0x0 = Reserved
- 0x1 = 1K bytes
- 0x2 = 2K bytes
- 0x3 = 6K bytes
- 0x4 = 112K bytes
- 0x5 = 4K bytes
- 0x6 = 80K bytes
- 0x7 = 160K bytes
- 0x8 = 8K bytes
- 0x9 = 16K bytes
- 0xA = 32K bytes
- 0xB = 64K bytes
- 0xC = 128K bytes
- 0xD = 256K bytes
- 0xE = 96K bytes
- 0xF = 512K bytes

- ARCH: Architecture Identifier

-

- NVPTYP: Nonvolatile Program Memory Type

- 0x0 = ROM
- 0x1 = ROMless or on-chip Flash
- 0x2 = Embedded Flash Memory
- 0x3 = ROM and Embedded Flash MemoryNVPSIZ is ROM size NVPSIZ2 is Flash size
- 0x4 = SRAM emulating ROM

- EXT: Extension Flag

- 0 = Chip ID has a single register definition without extension
- 1 = An extended Chip ID exists.

#### DBGU Chip ID Extension Register

Name: DBGU_EXID

Access: read-only

Address: 0xFFFFF244

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
EXID
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
EXID
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
EXID
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
EXID

- EXID: Chip ID Extension

-

#### DBGU Force NTRST Register

Name: DBGU_FNR

Access: read-write

Address: 0xFFFFF248

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | - | FNTRST

- FNTRST: Force NTRST

- 0 = NTRST of the ARM processor's TAP controller is driven by the power_on_reset signal.
- 1 = NTRST of the ARM processor's TAP controller is held low.

#### DBGU Receive Pointer Register

Name: DBGU_RPR

Access: read-write

Address: 0xFFFFF300

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RXPTR
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RXPTR
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RXPTR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RXPTR

- RXPTR: Receive Pointer Address

-

#### DBGU Receive Counter Register

Name: DBGU_RCR

Access: read-write

Address: 0xFFFFF304

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RXCTR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RXCTR

- RXCTR: Receive Counter Value

-

#### DBGU Transmit Pointer Register

Name: DBGU_TPR

Access: read-write

Address: 0xFFFFF308

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
TXPTR
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
TXPTR
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
TXPTR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TXPTR

- TXPTR: Transmit Pointer Address

-

#### DBGU Transmit Counter Register

Name: DBGU_TCR

Access: read-write

Address: 0xFFFFF30C

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
TXCTR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TXCTR

- TXCTR: Transmit Counter Value

-

#### DBGU Receive Next Pointer Register

Name: DBGU_RNPR

Access: read-write

Address: 0xFFFFF310

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RXNPTR
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RXNPTR
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RXNPTR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RXNPTR

- RXNPTR: Receive Next Pointer Address

-

#### DBGU Receive Next Counter Register

Name: DBGU_RNCR

Access: read-write

Address: 0xFFFFF314

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RXNCR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RXNCR

- RXNCR: Receive Next Counter Value

-

#### DBGU Transmit Next Pointer Register

Name: DBGU_TNPR

Access: read-write

Address: 0xFFFFF318

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
TXNPTR
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
TXNPTR
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
TXNPTR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TXNPTR

- TXNPTR: Transmit Next Pointer Address

-

#### DBGU Transmit Next Counter Register

Name: DBGU_TNCR

Access: read-write

Address: 0xFFFFF31C

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
TXNCR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TXNCR

- TXNCR: Transmit Next Counter Value

-

#### DBGU PDC Transfer Control Register

Name: DBGU_PTCR

Access: write-only

Address: 0xFFFFF320

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | TXTDIS | TXTEN
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | RXTDIS | RXTEN

- RXTEN: Receiver Transfer Enable

- 0 = No effect.
- 1 = Enables the receiver PDC transfer requests if RXTDIS is not set.

- RXTDIS: Receiver Transfer Disable

- 0 = No effect.
- 1 = Disables the receiver PDC transfer requests.

- TXTEN: Transmitter Transfer Enable

- 0 = No effect.
- 1 = Enables the transmitter PDC transfer requests.

- TXTDIS: Transmitter Transfer Disable

- 0 = No effect.
- 1 = Disables the transmitter PDC transfer requests.

#### DBGU PDC Transfer Status Register

Name: DBGU_PTSR

Access: read-only

Address: 0xFFFFF324

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | TXTEN
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | - | RXTEN

- RXTEN: Receiver Transfer Enable

- 0 = Receiver PDC transfer requests are disabled.
- 1 = Receiver PDC transfer requests are enabled.

- TXTEN: Transmitter Transfer Enable

- 0 = Transmitter PDC transfer requests are disabled.
- 1 = Transmitter PDC transfer requests are enabled.