# AT91SAM7L128 ADC

## Analog-to-digital Converter (ADC) User Interface

### Registers

Register Mapping
Address | Register | Name | Access | Reset
--- | --- | --- | --- | ---
0xFFFD8000 | Control Register | ADC_CR | write-only | -
0xFFFD8004 | Mode Register | ADC_MR | read-write | 0x00000000
0xFFFD8010 | Channel Enable Register | ADC_CHER | write-only | -
0xFFFD8014 | Channel Disable Register | ADC_CHDR | write-only | -
0xFFFD8018 | Channel Status Register | ADC_CHSR | read-only | 0x00000000
0xFFFD801C | Status Register | ADC_SR | read-only | 0x000C0000
0xFFFD8020 | Last Converted Data Register | ADC_LCDR | read-only | 0x00000000
0xFFFD8024 | Interrupt Enable Register | ADC_IER | write-only | -
0xFFFD8028 | Interrupt Disable Register | ADC_IDR | write-only | -
0xFFFD802C | Interrupt Mask Register | ADC_IMR | read-only | 0x00000000
0xFFFD8030 | Channel Data Register | ADC_CDR[7] | read-only | 0x00000000
0xFFFD8100 | Receive Pointer Register | ADC_RPR | read-write | 0x0
0xFFFD8104 | Receive Counter Register | ADC_RCR | read-write | 0x0
0xFFFD8108 | Transmit Pointer Register | ADC_TPR | read-write | 0x0
0xFFFD810C | Transmit Counter Register | ADC_TCR | read-write | 0x0
0xFFFD8110 | Receive Next Pointer Register | ADC_RNPR | read-write | 0x0
0xFFFD8114 | Receive Next Counter Register | ADC_RNCR | read-write | 0x0
0xFFFD8118 | Transmit Next Pointer Register | ADC_TNPR | read-write | 0x0
0xFFFD811C | Transmit Next Counter Register | ADC_TNCR | read-write | 0x0
0xFFFD8120 | PDC Transfer Control Register | ADC_PTCR | write-only | -
0xFFFD8124 | PDC Transfer Status Register | ADC_PTSR | read-only | 0x0

### Register Fields

#### ADC Control Register

Name: ADC_CR

Access: write-only

Address: 0xFFFD8000

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | START | SWRST

- SWRST: Software Reset

- 0 = No effect.
- 1 = Resets the ADC simulating a hardware reset.

- START: Start Conversion

- 0 = No effect.
- 1 = Begins analog-to-digital conversion.

#### ADC Mode Register

Name: ADC_MR

Access: read-write

Address: 0xFFFD8004

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | SHTIM
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | STARTUP
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
PRESCAL
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | SLEEP | LOWRES | TRGSEL | TRGEN

- TRGEN: Trigger Enable

- 0 = Hardware triggers are disabled. Starting a conversion is only possible by software.
- 1 = Hardware trigger selected by TRGSEL field is enabled.

- TRGSEL: Trigger Selection

- 0x0 = TIO Output of the Timer Counter Channel 0
- 0x1 = TIO Output of the Timer Counter Channel 1
- 0x2 = TIO Output of the Timer Counter Channel 2
- 0x3 = Reserved
- 0x4 = Reserved
- 0x5 = Reserved
- 0x6 = External trigger
- 0x7 = Reserved

- LOWRES: Resolution

- 0 = 10-bit resolution
- 1 = 8-bit resolution

- SLEEP: Sleep Mode

- 0 = Normal Mode
- 1 = Sleep Mode

- PRESCAL: Prescaler Rate Selection

-

- STARTUP: Start Up Time

-

- SHTIM: Sample & Hold Time

-

#### ADC Channel Enable Register

Name: ADC_CHER

Access: write-only

Address: 0xFFFD8010

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | CH3 | CH2 | CH1 | CH0

- CH0: Channel 0 Enable

- 0 = No effect.
- 1 = Enables the corresponding channel.

- CH1: Channel 1 Enable

- 0 = No effect.
- 1 = Enables the corresponding channel.

- CH2: Channel 2 Enable

- 0 = No effect.
- 1 = Enables the corresponding channel.

- CH3: Channel 3 Enable

- 0 = No effect.
- 1 = Enables the corresponding channel.

#### ADC Channel Disable Register

Name: ADC_CHDR

Access: write-only

Address: 0xFFFD8014

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | CH3 | CH2 | CH1 | CH0

- CH0: Channel 0 Disable

- 0 = No effect.
- 1 = Disables the corresponding channel.

- CH1: Channel 1 Disable

- 0 = No effect.
- 1 = Disables the corresponding channel.

- CH2: Channel 2 Disable

- 0 = No effect.
- 1 = Disables the corresponding channel.

- CH3: Channel 3 Disable

- 0 = No effect.
- 1 = Disables the corresponding channel.

#### ADC Channel Status Register

Name: ADC_CHSR

Access: read-only

Address: 0xFFFD8018

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | CH3 | CH2 | CH1 | CH0

- CH0: Channel 0 Status

- 0 = Corresponding channel is disabled.
- 1 = Corresponding channel is enabled.

- CH1: Channel 1 Status

- 0 = Corresponding channel is disabled.
- 1 = Corresponding channel is enabled.

- CH2: Channel 2 Status

- 0 = Corresponding channel is disabled.
- 1 = Corresponding channel is enabled.

- CH3: Channel 3 Status

- 0 = Corresponding channel is disabled.
- 1 = Corresponding channel is enabled.

#### ADC Status Register

Name: ADC_SR

Access: read-only

Address: 0xFFFD801C

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | RXBUFF | ENDRX | GOVRE | DRDY
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | OVRE3 | OVRE2 | OVRE1 | OVRE0
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | EOC3 | EOC2 | EOC1 | EOC0

- EOC0: End of Conversion 0

- 0 = Corresponding analog channel is disabled, or the conversion is not finished.
- 1 = Corresponding analog channel is enabled and conversion is complete.

- EOC1: End of Conversion 1

- 0 = Corresponding analog channel is disabled, or the conversion is not finished.
- 1 = Corresponding analog channel is enabled and conversion is complete.

- EOC2: End of Conversion 2

- 0 = Corresponding analog channel is disabled, or the conversion is not finished.
- 1 = Corresponding analog channel is enabled and conversion is complete.

- EOC3: End of Conversion 3

- 0 = Corresponding analog channel is disabled, or the conversion is not finished.
- 1 = Corresponding analog channel is enabled and conversion is complete.

- OVRE0: Overrun Error 0

- 0 = No overrun error on the corresponding channel since the last read of ADC_SR.
- 1 = There has been an overrun error on the corresponding channel since the last read of ADC_SR.

- OVRE1: Overrun Error 1

- 0 = No overrun error on the corresponding channel since the last read of ADC_SR.
- 1 = There has been an overrun error on the corresponding channel since the last read of ADC_SR.

- OVRE2: Overrun Error 2

- 0 = No overrun error on the corresponding channel since the last read of ADC_SR.
- 1 = There has been an overrun error on the corresponding channel since the last read of ADC_SR.

- OVRE3: Overrun Error 3

- 0 = No overrun error on the corresponding channel since the last read of ADC_SR.
- 1 = There has been an overrun error on the corresponding channel since the last read of ADC_SR.

- DRDY: Data Ready

- 0 = No data has been converted since the last read of ADC_LCDR.
- 1 = At least one data has been converted and is available in ADC_LCDR.

- GOVRE: General Overrun Error

- 0 = No General Overrun Error occurred since the last read of ADC_SR.
- 1 = At least one General Overrun Error has occurred since the last read of ADC_SR.

- ENDRX: End of RX Buffer

- 0 = The Receive Counter Register has not reached 0 since the last write in ADC_RCR or ADC_RNCR.
- 1 = The Receive Counter Register has reached 0 since the last write in ADC_RCR or ADC_RNCR.

- RXBUFF: RX Buffer Full

- 0 = ADC_RCR or ADC_RNCR have a value other than 0.
- 1 = Both ADC_RCR and ADC_RNCR have a value of 0.

#### ADC Last Converted Data Register

Name: ADC_LCDR

Access: read-only

Address: 0xFFFD8020

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | LDATA
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
LDATA

- LDATA: Last Data Converted

-

#### ADC Interrupt Enable Register

Name: ADC_IER

Access: write-only

Address: 0xFFFD8024

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | RXBUFF | ENDRX | GOVRE | DRDY
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | OVRE3 | OVRE2 | OVRE1 | OVRE0
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | EOC3 | EOC2 | EOC1 | EOC0

- EOC0: End of Conversion Interrupt Enable 0

- 0 = No effect.
- 1 = Enables the corresponding interrupt.

- EOC1: End of Conversion Interrupt Enable 1

- 0 = No effect.
- 1 = Enables the corresponding interrupt.

- EOC2: End of Conversion Interrupt Enable 2

- 0 = No effect.
- 1 = Enables the corresponding interrupt.

- EOC3: End of Conversion Interrupt Enable 3

- 0 = No effect.
- 1 = Enables the corresponding interrupt.

- OVRE0: Overrun Error Interrupt Enable 0

- 0 = No effect.
- 1 = Enables the corresponding interrupt.

- OVRE1: Overrun Error Interrupt Enable 1

- 0 = No effect.
- 1 = Enables the corresponding interrupt.

- OVRE2: Overrun Error Interrupt Enable 2

- 0 = No effect.
- 1 = Enables the corresponding interrupt.

- OVRE3: Overrun Error Interrupt Enable 3

- 0 = No effect.
- 1 = Enables the corresponding interrupt.

- DRDY: Data Ready Interrupt Enable

- 0 = No effect.
- 1 = Enables the corresponding interrupt.

- GOVRE: General Overrun Error Interrupt Enable

- 0 = No effect.
- 1 = Enables the corresponding interrupt.

- ENDRX: End of Receive Buffer Interrupt Enable

- 0 = No effect.
- 1 = Enables the corresponding interrupt.

- RXBUFF: Receive Buffer Full Interrupt Enable

- 0 = No effect.
- 1 = Enables the corresponding interrupt.

#### ADC Interrupt Disable Register

Name: ADC_IDR

Access: write-only

Address: 0xFFFD8028

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | RXBUFF | ENDRX | GOVRE | DRDY
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | OVRE3 | OVRE2 | OVRE1 | OVRE0
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | EOC3 | EOC2 | EOC1 | EOC0

- EOC0: End of Conversion Interrupt Disable 0

- 0 = No effect.
- 1 = Disables the corresponding interrupt.

- EOC1: End of Conversion Interrupt Disable 1

- 0 = No effect.
- 1 = Disables the corresponding interrupt.

- EOC2: End of Conversion Interrupt Disable 2

- 0 = No effect.
- 1 = Disables the corresponding interrupt.

- EOC3: End of Conversion Interrupt Disable 3

- 0 = No effect.
- 1 = Disables the corresponding interrupt.

- OVRE0: Overrun Error Interrupt Disable 0

- 0 = No effect.
- 1 = Disables the corresponding interrupt.

- OVRE1: Overrun Error Interrupt Disable 1

- 0 = No effect.
- 1 = Disables the corresponding interrupt.

- OVRE2: Overrun Error Interrupt Disable 2

- 0 = No effect.
- 1 = Disables the corresponding interrupt.

- OVRE3: Overrun Error Interrupt Disable 3

- 0 = No effect.
- 1 = Disables the corresponding interrupt.

- DRDY: Data Ready Interrupt Disable

- 0 = No effect.
- 1 = Disables the corresponding interrupt.

- GOVRE: General Overrun Error Interrupt Disable

- 0 = No effect.
- 1 = Disables the corresponding interrupt.

- ENDRX: End of Receive Buffer Interrupt Disable

- 0 = No effect.
- 1 = Disables the corresponding interrupt.

- RXBUFF: Receive Buffer Full Interrupt Disable

- 0 = No effect.
- 1 = Disables the corresponding interrupt.

#### ADC Interrupt Mask Register

Name: ADC_IMR

Access: read-only

Address: 0xFFFD802C

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | RXBUFF | ENDRX | GOVRE | DRDY
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | OVRE3 | OVRE2 | OVRE1 | OVRE0
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | EOC3 | EOC2 | EOC1 | EOC0

- EOC0: End of Conversion Interrupt Mask 0

- 0 = The corresponding interrupt is disabled.
- 1 = The corresponding interrupt is enabled.

- EOC1: End of Conversion Interrupt Mask 1

- 0 = The corresponding interrupt is disabled.
- 1 = The corresponding interrupt is enabled.

- EOC2: End of Conversion Interrupt Mask 2

- 0 = The corresponding interrupt is disabled.
- 1 = The corresponding interrupt is enabled.

- EOC3: End of Conversion Interrupt Mask 3

- 0 = The corresponding interrupt is disabled.
- 1 = The corresponding interrupt is enabled.

- OVRE0: Overrun Error Interrupt Mask 0

- 0 = The corresponding interrupt is disabled.
- 1 = The corresponding interrupt is enabled.

- OVRE1: Overrun Error Interrupt Mask 1

- 0 = The corresponding interrupt is disabled.
- 1 = The corresponding interrupt is enabled.

- OVRE2: Overrun Error Interrupt Mask 2

- 0 = The corresponding interrupt is disabled.
- 1 = The corresponding interrupt is enabled.

- OVRE3: Overrun Error Interrupt Mask 3

- 0 = The corresponding interrupt is disabled.
- 1 = The corresponding interrupt is enabled.

- DRDY: Data Ready Interrupt Mask

- 0 = The corresponding interrupt is disabled.
- 1 = The corresponding interrupt is enabled.

- GOVRE: General Overrun Error Interrupt Mask

- 0 = The corresponding interrupt is disabled.
- 1 = The corresponding interrupt is enabled.

- ENDRX: End of Receive Buffer Interrupt Mask

- 0 = The corresponding interrupt is disabled.
- 1 = The corresponding interrupt is enabled.

- RXBUFF: Receive Buffer Full Interrupt Mask

- 0 = The corresponding interrupt is disabled.
- 1 = The corresponding interrupt is enabled.

#### ADC Channel Data Register

Name: ADC_CDR[0:6]

Access: read-only

Address: 0xFFFD8030

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | DATA
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
DATA

- DATA: Converted Data

-

#### ADC Receive Pointer Register

Name: ADC_RPR

Access: read-write

Address: 0xFFFD8100

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RXPTR
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RXPTR
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RXPTR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RXPTR

- RXPTR: Receive Pointer Address

-

#### ADC Receive Counter Register

Name: ADC_RCR

Access: read-write

Address: 0xFFFD8104

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RXCTR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RXCTR

- RXCTR: Receive Counter Value

-

#### ADC Transmit Pointer Register

Name: ADC_TPR

Access: read-write

Address: 0xFFFD8108

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
TXPTR
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
TXPTR
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
TXPTR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TXPTR

- TXPTR: Transmit Pointer Address

-

#### ADC Transmit Counter Register

Name: ADC_TCR

Access: read-write

Address: 0xFFFD810C

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
TXCTR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TXCTR

- TXCTR: Transmit Counter Value

-

#### ADC Receive Next Pointer Register

Name: ADC_RNPR

Access: read-write

Address: 0xFFFD8110

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RXNPTR
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RXNPTR
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RXNPTR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RXNPTR

- RXNPTR: Receive Next Pointer Address

-

#### ADC Receive Next Counter Register

Name: ADC_RNCR

Access: read-write

Address: 0xFFFD8114

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RXNCR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RXNCR

- RXNCR: Receive Next Counter Value

-

#### ADC Transmit Next Pointer Register

Name: ADC_TNPR

Access: read-write

Address: 0xFFFD8118

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
TXNPTR
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
TXNPTR
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
TXNPTR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TXNPTR

- TXNPTR: Transmit Next Pointer Address

-

#### ADC Transmit Next Counter Register

Name: ADC_TNCR

Access: read-write

Address: 0xFFFD811C

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
TXNCR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TXNCR

- TXNCR: Transmit Next Counter Value

-

#### ADC PDC Transfer Control Register

Name: ADC_PTCR

Access: write-only

Address: 0xFFFD8120

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | TXTDIS | TXTEN
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | RXTDIS | RXTEN

- RXTEN: Receiver Transfer Enable

- 0 = No effect.
- 1 = Enables the receiver PDC transfer requests if RXTDIS is not set.

- RXTDIS: Receiver Transfer Disable

- 0 = No effect.
- 1 = Disables the receiver PDC transfer requests.

- TXTEN: Transmitter Transfer Enable

- 0 = No effect.
- 1 = Enables the transmitter PDC transfer requests.

- TXTDIS: Transmitter Transfer Disable

- 0 = No effect.
- 1 = Disables the transmitter PDC transfer requests.

#### ADC PDC Transfer Status Register

Name: ADC_PTSR

Access: read-only

Address: 0xFFFD8124

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | TXTEN
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | - | RXTEN

- RXTEN: Receiver Transfer Enable

- 0 = Receiver PDC transfer requests are disabled.
- 1 = Receiver PDC transfer requests are enabled.

- TXTEN: Transmitter Transfer Enable

- 0 = Transmitter PDC transfer requests are disabled.
- 1 = Transmitter PDC transfer requests are enabled.