# AT91SAM7L128 SLCDC

## Segment LCD Controller (SLCDC) User Interface

### Registers

Register Mapping
Address | Register | Name | Access | Reset
--- | --- | --- | --- | ---
0xFFFB4000 | SLCDC Control Register | SLCDC_CR | write-only | -
0xFFFB4004 | SLCDC Mode Register | SLCDC_MR | read-write | 0x0
0xFFFB4008 | SLCDC Frame Rate Register | SLCDC_FRR | read-write | 0x0
0xFFFB400C | SLCDC Display Register | SLCDC_DR | read-write | 0x0
0xFFFB4010 | SLCDC Status Register | SLCDC_SR | read-only | 0x0
0xFFFB4020 | SLCDC Interrupt Enable Register | SLCDC_IER | write-only | -
0xFFFB4024 | SLCDC Interrupt Disable Register | SLCDC_IDR | write-only | -
0xFFFB4028 | SLCDC Interrupt Mask Register | SLCDC_IMR | write-only | -
0xFFFB402C | SLCDC Interrupt Status Register | SLCDC_ISR | read-only | 0x0
0xFFFB4200 | SLCDC Memory Register | SLCDC_MEM | read-write | 0x0

### Register Fields

#### SLCDC SLCDC Control Register

Name: SLCDC_CR

Access: write-only

Address: 0xFFFB4000

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | SWRST | - | LCDDIS | LCDEN

- LCDEN: Enable the LCDC

- 0 = No effect.
- 1 = The SLCDC is enabled

- LCDDIS: Disable LCDC

- 0 = No effect.
- 1 = The SLCDC is disabled.

- SWRST: Software Reset

- 0 = No effect.
- 1 = Equivalent to a power-up reset. When this command is performed, the SLCDC1 immediately ties all segments end commons lines to values corresponding to a "ground voltage".

#### SLCDC SLCDC Mode Register

Name: SLCDC_MR

Access: read-write

Address: 0xFFFB4004

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | LPMODE
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | BIAS | BUFTIME
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | SEGSEL
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | COMSEL

- COMSEL: Selection of the Number of Commons

-

- SEGSEL: Selection of the Number of Segments

-

- BUFTIME: Buffer On-Time

- 0x0 = 0%
- 0x1 = 2 x tSCLK
- 0x2 = 4 x tSCLK
- 0x3 = 8 x tSCLK
- 0x4 = 16 x tSCLK
- 0x5 = 32 x tSCLK
- 0x6 = 64 x tSCLK
- 0x7 = 128 x tSCLK
- 0x8 = 50%
- 0x9 = 100%

- BIAS: LCD Display Configuration

- 0x0 = 1
- 0x1 = 1/2
- 0x2 = 1/3
- 0x3 = 1/4

- LPMODE: Low Power Mode (Taken into account from the next begin of frame.)

- 0 = Normal Mode.
- 1 = Low Power Waveform is enabled.

#### SLCDC SLCDC Frame Rate Register

Name: SLCDC_FRR

Access: read-write

Address: 0xFFFB4008

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | DIV
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | PRESC

- PRESC

-

- DIV: Clock Division

- 0x0 = 1
- 0x1 = 2
- 0x2 = 3
- 0x3 = 4
- 0x4 = 5
- 0x5 = 6
- 0x6 = 7
- 0x7 = 8

#### SLCDC SLCDC Display Register

Name: SLCDC_DR

Access: read-write

Address: 0xFFFB400C

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
LCDBLKFREQ
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | DISPMODE

- DISPMODE: Display Mode Register

- 0x0 = Normal Mode: Latched data are displayed.
- 0x1 = Force Off Mode: All pixels are invisible. (The SLCDC memory is unchanged.)
- 0x2 = Force On Mode All pixels are visible. (The SLCDC memory is unchanged.)
- 0x3 = Blinking Mode: All pixels are alternately turned off to the predefined state in SLCDC memory at LCDBLKFREQ frequency. (The SLCDC memory is unchanged.)
- 0x4 = Inverted Mode: All pixels are set in the inverted state as defined in SLCDC memory. (The SLCDC memory is unchanged.)
- 0x5 = Inverted Blinking Mode: All pixels are alternately turned off to the predefined opposite state in SLCDC memory at LCDBLKFREQ frequency. (The SLCDC memory is unchanged.)
- 0x6 = User Buffer Only Load Mode: Blocks the automatic transfer from User Buffer to Display Buffer.
- 0x7 = Buffer Swap Mode: All pixels are alternatively assigned to the state defined in the User Buffer, then to the state defined in the Display Buffer at LCDBLKFREQ frequency.

- LCDBLKFREQ: LCD Blinking Frequency Selection

-

#### SLCDC SLCDC Status Register

Name: SLCDC_SR

Access: read-only

Address: 0xFFFB4010

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | - | ENA

- ENA: Enable Status (Automatically Set/Reset)

- 0 = The SLCDC1 is disabled.
- 1 = The SLCDC1 is enabled.

#### SLCDC SLCDC Interrupt Enable Register

Name: SLCDC_IER

Access: write-only

Address: 0xFFFB4020

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | DIS | - | ENDFRAME

- ENDFRAME: End of Frame Interrupt Enable

- 0 = No effect.
- 1 = Enables the corresponding interrupt.

- DIS: Disable Interrupt Enable

- 0 = No effect.
- 1 = Enables the corresponding interrupt.

#### SLCDC SLCDC Interrupt Disable Register

Name: SLCDC_IDR

Access: write-only

Address: 0xFFFB4024

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | DIS | - | ENDFRAME

- ENDFRAME: End of Frame Interrupt Disable

- 0 = No effect.
- 1 = Disables the corresponding interrupt.

- DIS: Disable Interrupt Disable

- 0 = No effect.
- 1 = Disables the corresponding interrupt.

#### SLCDC SLCDC Interrupt Mask Register

Name: SLCDC_IMR

Access: write-only

Address: 0xFFFB4028

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | DIS | - | ENDFRAME

- ENDFRAME: End of Frame Interrupt Mask

- 0 = The corresponding interrupt is not enabled.
- 1 = The corresponding interrupt is enabled.

- DIS: Disable Interrupt Mask

- 0 = The corresponding interrupt is not enabled.
- 1 = The corresponding interrupt is enabled.

#### SLCDC SLCDC Interrupt Status Register

Name: SLCDC_ISR

Access: read-only

Address: 0xFFFB402C

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | DIS | - | ENDFRAME

- ENDFRAME: End of Frame Interrupt Status

- 0 = End of Frame Interrupt has not occurred since the last read of the Interrupt Status Register.
- 1 = End of Frame Interrupt has occurred since the last read of the Interrupt Status Register.

- DIS: Disable Interrupt Status

- 0 = Disable Interrupt has not occurred since the last read of the Interrupt Status Register
- 1 = Disable Interrupt has occurred since the last read of the Interrupt Status Register.

#### SLCDC SLCDC Memory Register

Name: SLCDC_MEM

Access: read-write

Address: 0xFFFB4200

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | - | -