AT91SAM7L128 PWM

Pulse Width Modulation Controller (PWM) User Interface

Registers

Register Mapping

Address	Register	Name	Access	Reset
0xFFFCC000	PWM Mode Register	PWM_MR	read-write	-
0xFFFCC004	PWM Enable Register	PWM_ENA	write-only	-
0xFFFCC008	PWM Disable Register	PWM_DIS	write-only	-
0xFFFCC00C	PWM Status Register	PWM_SR	read-only	-
0xFFFCC010	PWM Interrupt Enable Register	PWM_IER	write-only	-
0xFFFCC014	PWM Interrupt Disable Register	PWM_IDR	write-only	-
0xFFFCC018	PWM Interrupt Mask Register	PWM_IMR	read-only	-
0xFFFCC01C	PWM Interrupt Status Register	PWM_ISR	read-only	-
0xFFFCC200	PWM Channel Mode Register (ch_num = 0)	PWM_CMR0	read-write	0x0
0xFFFCC204	PWM Channel Duty Cycle Register (ch_num = 0)	PWM_CDTY0	read-write	0x0
0xFFFCC208	PWM Channel Period Register (ch_num = 0)	PWM_CPRD0	read-write	0x0
0xFFFCC20C	PWM Channel Counter Register (ch_num = 0)	PWM_CCNT0	read-only	0x0
0xFFFCC210	PWM Channel Update Register (ch_num = 0)	PWM_CUPD0	write-only	-
0xFFFCC220	PWM Channel Mode Register (ch_num = 1)	PWM_CMR1	read-write	0x0
0xFFFCC224	PWM Channel Duty Cycle Register (ch_num = 1)	PWM_CDTY1	read-write	0x0
0xFFFCC228	PWM Channel Period Register (ch_num = 1)	PWM_CPRD1	read-write	0x0
0xFFFCC22C	PWM Channel Counter Register (ch_num = 1)	PWM_CCNT1	read-only	0x0
0xFFFCC230	PWM Channel Update Register (ch_num = 1)	PWM_CUPD1	write-only	-
0xFFFCC240	PWM Channel Mode Register (ch_num = 2)	PWM_CMR2	read-write	0x0
0xFFFCC244	PWM Channel Duty Cycle Register (ch_num = 2)	PWM_CDTY2	read-write	0x0
0xFFFCC248	PWM Channel Period Register (ch_num = 2)	PWM_CPRD2	read-write	0x0
0xFFFCC24C	PWM Channel Counter Register (ch_num = 2)	PWM_CCNT2	read-only	0x0
0xFFFCC250	PWM Channel Update Register (ch_num = 2)	PWM_CUPD2	write-only	-
0xFFFCC260	PWM Channel Mode Register (ch_num = 3)	PWM_CMR3	read-write	0x0
0xFFFCC264	PWM Channel Duty Cycle Register (ch_num = 3)	PWM_CDTY3	read-write	0x0
0xFFFCC268	PWM Channel Period Register (ch_num = 3)	PWM_CPRD3	read-write	0x0
0xFFFCC26C	PWM Channel Counter Register (ch_num = 3)	PWM_CCNT3	read-only	0x0
0xFFFCC270	PWM Channel Update Register (ch_num = 3)	PWM_CUPD3	write-only	-

Register Fields

PWM PWM Mode Register

Name: PWM_MR

Access: read-write

Address: 0xFFFCC000

31	30	29	28	27	26	25	24
-	-	-	-	PREB
23	22	21	20	19	18	17	16
DIVB
15	14	13	12	11	10	9	8
-	-	-	-	PREA
7	6	5	4	3	2	1	0
DIVA

• DIVA: CLKA, CLKB Divide Factor

-

• PREA
• 0x0 = MCK.
• 0x1 = MCK/2
• 0x2 = MCK/4
• 0x3 = MCK/8
• 0x4 = MCK/16
• 0x5 = MCK/32
• 0x6 = MCK/64
• 0x7 = MCK/128
• 0x8 = MCK/256
• 0x9 = MCK/512
• 0xA = MCK/1024
• DIVB: CLKA, CLKB Divide Factor

-

• PREB
• 0x0 = MCK.
• 0x1 = MCK/2
• 0x2 = MCK/4
• 0x3 = MCK/8
• 0x4 = MCK/16
• 0x5 = MCK/32
• 0x6 = MCK/64
• 0x7 = MCK/128
• 0x8 = MCK/256
• 0x9 = MCK/512
• 0xA = MCK/1024

PWM PWM Enable Register

Name: PWM_ENA

Access: write-only

Address: 0xFFFCC004

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
-	-	-	-	CHID3	CHID2	CHID1	CHID0

• CHID0: Channel ID
• 0 = No effect.
• 1 = Enable PWM output for channel x.
• CHID1: Channel ID
• 0 = No effect.
• 1 = Enable PWM output for channel x.
• CHID2: Channel ID
• 0 = No effect.
• 1 = Enable PWM output for channel x.
• CHID3: Channel ID
• 0 = No effect.
• 1 = Enable PWM output for channel x.

PWM PWM Disable Register

Name: PWM_DIS

Access: write-only

Address: 0xFFFCC008

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
-	-	-	-	CHID3	CHID2	CHID1	CHID0

• CHID0: Channel ID
• 0 = No effect.
• 1 = Disable PWM output for channel x.
• CHID1: Channel ID
• 0 = No effect.
• 1 = Disable PWM output for channel x.
• CHID2: Channel ID
• 0 = No effect.
• 1 = Disable PWM output for channel x.
• CHID3: Channel ID
• 0 = No effect.
• 1 = Disable PWM output for channel x.

PWM PWM Status Register

Name: PWM_SR

Access: read-only

Address: 0xFFFCC00C

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
-	-	-	-	CHID3	CHID2	CHID1	CHID0

• CHID0: Channel ID
• 0 = PWM output for channel x is disabled.
• 1 = PWM output for channel x is enabled.
• CHID1: Channel ID
• 0 = PWM output for channel x is disabled.
• 1 = PWM output for channel x is enabled.
• CHID2: Channel ID
• 0 = PWM output for channel x is disabled.
• 1 = PWM output for channel x is enabled.
• CHID3: Channel ID
• 0 = PWM output for channel x is disabled.
• 1 = PWM output for channel x is enabled.

PWM PWM Interrupt Enable Register

Name: PWM_IER

Access: write-only

Address: 0xFFFCC010

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
-	-	-	-	CHID3	CHID2	CHID1	CHID0

• CHID0: Channel ID.
• 0 = No effect.
• 1 = Enable interrupt for PWM channel x.
• CHID1: Channel ID.
• 0 = No effect.
• 1 = Enable interrupt for PWM channel x.
• CHID2: Channel ID.
• 0 = No effect.
• 1 = Enable interrupt for PWM channel x.
• CHID3: Channel ID.
• 0 = No effect.
• 1 = Enable interrupt for PWM channel x.

PWM PWM Interrupt Disable Register

Name: PWM_IDR

Access: write-only

Address: 0xFFFCC014

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
-	-	-	-	CHID3	CHID2	CHID1	CHID0

• CHID0: Channel ID.
• 0 = No effect.
• 1 = Disable interrupt for PWM channel x.
• CHID1: Channel ID.
• 0 = No effect.
• 1 = Disable interrupt for PWM channel x.
• CHID2: Channel ID.
• 0 = No effect.
• 1 = Disable interrupt for PWM channel x.
• CHID3: Channel ID.
• 0 = No effect.
• 1 = Disable interrupt for PWM channel x.

PWM PWM Interrupt Mask Register

Name: PWM_IMR

Access: read-only

Address: 0xFFFCC018

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
-	-	-	-	CHID3	CHID2	CHID1	CHID0

• CHID0: Channel ID.
• 0 = Interrupt for PWM channel x is disabled.
• 1 = Interrupt for PWM channel x is enabled.
• CHID1: Channel ID.
• 0 = Interrupt for PWM channel x is disabled.
• 1 = Interrupt for PWM channel x is enabled.
• CHID2: Channel ID.
• 0 = Interrupt for PWM channel x is disabled.
• 1 = Interrupt for PWM channel x is enabled.
• CHID3: Channel ID.
• 0 = Interrupt for PWM channel x is disabled.
• 1 = Interrupt for PWM channel x is enabled.

PWM PWM Interrupt Status Register

Name: PWM_ISR

Access: read-only

Address: 0xFFFCC01C

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
-	-	-	-	CHID3	CHID2	CHID1	CHID0

• CHID0: Channel ID
• 0 = No new channel period has been achieved since the last read of the PWM_ISR register.
• 1 = At least one new channel period has been achieved since the last read of the PWM_ISR register.
• CHID1: Channel ID
• 0 = No new channel period has been achieved since the last read of the PWM_ISR register.
• 1 = At least one new channel period has been achieved since the last read of the PWM_ISR register.
• CHID2: Channel ID
• 0 = No new channel period has been achieved since the last read of the PWM_ISR register.
• 1 = At least one new channel period has been achieved since the last read of the PWM_ISR register.
• CHID3: Channel ID
• 0 = No new channel period has been achieved since the last read of the PWM_ISR register.
• 1 = At least one new channel period has been achieved since the last read of the PWM_ISR register.

PWM PWM Channel Mode Register (ch_num = 0)

Name: PWM_CMR0

Access: read-write

Address: 0xFFFCC200

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	CPD	CPOL	CALG
7	6	5	4	3	2	1	0
-	-	-	-	CPRE

• CPRE: Channel Pre-scaler
• 0x0 = MCK
• 0x1 = MCK/2
• 0x2 = MCK/4
• 0x3 = MCK/8
• 0x4 = MCK/16
• 0x5 = MCK/32
• 0x6 = MCK/64
• 0x7 = MCK/128
• 0x8 = MCK/256
• 0x9 = MCK/512
• 0xA = MCK/1024
• 0xB = CLKA
• 0xC = CLKB
• CALG: Channel Alignment
• 0 = The period is left aligned.
• 1 = The period is center aligned.
• CPOL: Channel Polarity
• 0 = The output waveform starts at a low level.
• 1 = The output waveform starts at a high level.
• CPD: Channel Update Period
• 0 = Writing to the PWM_CUPDx will modify the duty cycle at the next period start event.
• 1 = Writing to the PWM_CUPDx will modify the period at the next period start event.

PWM PWM Channel Duty Cycle Register (ch_num = 0)

Name: PWM_CDTY0

Access: read-write

Address: 0xFFFCC204

31	30	29	28	27	26	25	24
CDTY
23	22	21	20	19	18	17	16
CDTY
15	14	13	12	11	10	9	8
CDTY
7	6	5	4	3	2	1	0
CDTY

• CDTY: Channel Duty Cycle

-

PWM PWM Channel Period Register (ch_num = 0)

Name: PWM_CPRD0

Access: read-write

Address: 0xFFFCC208

31	30	29	28	27	26	25	24
CPRD
23	22	21	20	19	18	17	16
CPRD
15	14	13	12	11	10	9	8
CPRD
7	6	5	4	3	2	1	0
CPRD

• CPRD: Channel Period

-

PWM PWM Channel Counter Register (ch_num = 0)

Name: PWM_CCNT0

Access: read-only

Address: 0xFFFCC20C

31	30	29	28	27	26	25	24
CNT
23	22	21	20	19	18	17	16
CNT
15	14	13	12	11	10	9	8
CNT
7	6	5	4	3	2	1	0
CNT

• CNT: Channel Counter Register

-

PWM PWM Channel Update Register (ch_num = 0)

Name: PWM_CUPD0

Access: write-only

Address: 0xFFFCC210

31	30	29	28	27	26	25	24
CUPD
23	22	21	20	19	18	17	16
CUPD
15	14	13	12	11	10	9	8
CUPD
7	6	5	4	3	2	1	0
CUPD

• CUPD

-

PWM PWM Channel Mode Register (ch_num = 1)

Name: PWM_CMR1

Access: read-write

Address: 0xFFFCC220

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	CPD	CPOL	CALG
7	6	5	4	3	2	1	0
-	-	-	-	CPRE

• CPRE: Channel Pre-scaler
• 0x0 = MCK
• 0x1 = MCK/2
• 0x2 = MCK/4
• 0x3 = MCK/8
• 0x4 = MCK/16
• 0x5 = MCK/32
• 0x6 = MCK/64
• 0x7 = MCK/128
• 0x8 = MCK/256
• 0x9 = MCK/512
• 0xA = MCK/1024
• 0xB = CLKA
• 0xC = CLKB
• CALG: Channel Alignment
• 0 = The period is left aligned.
• 1 = The period is center aligned.
• CPOL: Channel Polarity
• 0 = The output waveform starts at a low level.
• 1 = The output waveform starts at a high level.
• CPD: Channel Update Period
• 0 = Writing to the PWM_CUPDx will modify the duty cycle at the next period start event.
• 1 = Writing to the PWM_CUPDx will modify the period at the next period start event.

PWM PWM Channel Duty Cycle Register (ch_num = 1)

Name: PWM_CDTY1

Access: read-write

Address: 0xFFFCC224

31	30	29	28	27	26	25	24
CDTY
23	22	21	20	19	18	17	16
CDTY
15	14	13	12	11	10	9	8
CDTY
7	6	5	4	3	2	1	0
CDTY

• CDTY: Channel Duty Cycle

-

PWM PWM Channel Period Register (ch_num = 1)

Name: PWM_CPRD1

Access: read-write

Address: 0xFFFCC228

31	30	29	28	27	26	25	24
CPRD
23	22	21	20	19	18	17	16
CPRD
15	14	13	12	11	10	9	8
CPRD
7	6	5	4	3	2	1	0
CPRD

• CPRD: Channel Period

-

PWM PWM Channel Counter Register (ch_num = 1)

Name: PWM_CCNT1

Access: read-only

Address: 0xFFFCC22C

31	30	29	28	27	26	25	24
CNT
23	22	21	20	19	18	17	16
CNT
15	14	13	12	11	10	9	8
CNT
7	6	5	4	3	2	1	0
CNT

• CNT: Channel Counter Register

-

PWM PWM Channel Update Register (ch_num = 1)

Name: PWM_CUPD1

Access: write-only

Address: 0xFFFCC230

31	30	29	28	27	26	25	24
CUPD
23	22	21	20	19	18	17	16
CUPD
15	14	13	12	11	10	9	8
CUPD
7	6	5	4	3	2	1	0
CUPD

• CUPD

-

PWM PWM Channel Mode Register (ch_num = 2)

Name: PWM_CMR2

Access: read-write

Address: 0xFFFCC240

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	CPD	CPOL	CALG
7	6	5	4	3	2	1	0
-	-	-	-	CPRE

• CPRE: Channel Pre-scaler
• 0x0 = MCK
• 0x1 = MCK/2
• 0x2 = MCK/4
• 0x3 = MCK/8
• 0x4 = MCK/16
• 0x5 = MCK/32
• 0x6 = MCK/64
• 0x7 = MCK/128
• 0x8 = MCK/256
• 0x9 = MCK/512
• 0xA = MCK/1024
• 0xB = CLKA
• 0xC = CLKB
• CALG: Channel Alignment
• 0 = The period is left aligned.
• 1 = The period is center aligned.
• CPOL: Channel Polarity
• 0 = The output waveform starts at a low level.
• 1 = The output waveform starts at a high level.
• CPD: Channel Update Period
• 0 = Writing to the PWM_CUPDx will modify the duty cycle at the next period start event.
• 1 = Writing to the PWM_CUPDx will modify the period at the next period start event.

PWM PWM Channel Duty Cycle Register (ch_num = 2)

Name: PWM_CDTY2

Access: read-write

Address: 0xFFFCC244

31	30	29	28	27	26	25	24
CDTY
23	22	21	20	19	18	17	16
CDTY
15	14	13	12	11	10	9	8
CDTY
7	6	5	4	3	2	1	0
CDTY

• CDTY: Channel Duty Cycle

-

PWM PWM Channel Period Register (ch_num = 2)

Name: PWM_CPRD2

Access: read-write

Address: 0xFFFCC248

31	30	29	28	27	26	25	24
CPRD
23	22	21	20	19	18	17	16
CPRD
15	14	13	12	11	10	9	8
CPRD
7	6	5	4	3	2	1	0
CPRD

• CPRD: Channel Period

-

PWM PWM Channel Counter Register (ch_num = 2)

Name: PWM_CCNT2

Access: read-only

Address: 0xFFFCC24C

31	30	29	28	27	26	25	24
CNT
23	22	21	20	19	18	17	16
CNT
15	14	13	12	11	10	9	8
CNT
7	6	5	4	3	2	1	0
CNT

• CNT: Channel Counter Register

-

PWM PWM Channel Update Register (ch_num = 2)

Name: PWM_CUPD2

Access: write-only

Address: 0xFFFCC250

31	30	29	28	27	26	25	24
CUPD
23	22	21	20	19	18	17	16
CUPD
15	14	13	12	11	10	9	8
CUPD
7	6	5	4	3	2	1	0
CUPD

• CUPD

-

PWM PWM Channel Mode Register (ch_num = 3)

Name: PWM_CMR3

Access: read-write

Address: 0xFFFCC260

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	CPD	CPOL	CALG
7	6	5	4	3	2	1	0
-	-	-	-	CPRE

• CPRE: Channel Pre-scaler
• 0x0 = MCK
• 0x1 = MCK/2
• 0x2 = MCK/4
• 0x3 = MCK/8
• 0x4 = MCK/16
• 0x5 = MCK/32
• 0x6 = MCK/64
• 0x7 = MCK/128
• 0x8 = MCK/256
• 0x9 = MCK/512
• 0xA = MCK/1024
• 0xB = CLKA
• 0xC = CLKB
• CALG: Channel Alignment
• 0 = The period is left aligned.
• 1 = The period is center aligned.
• CPOL: Channel Polarity
• 0 = The output waveform starts at a low level.
• 1 = The output waveform starts at a high level.
• CPD: Channel Update Period
• 0 = Writing to the PWM_CUPDx will modify the duty cycle at the next period start event.
• 1 = Writing to the PWM_CUPDx will modify the period at the next period start event.

PWM PWM Channel Duty Cycle Register (ch_num = 3)

Name: PWM_CDTY3

Access: read-write

Address: 0xFFFCC264

31	30	29	28	27	26	25	24
CDTY
23	22	21	20	19	18	17	16
CDTY
15	14	13	12	11	10	9	8
CDTY
7	6	5	4	3	2	1	0
CDTY

• CDTY: Channel Duty Cycle

-

PWM PWM Channel Period Register (ch_num = 3)

Name: PWM_CPRD3

Access: read-write

Address: 0xFFFCC268

31	30	29	28	27	26	25	24
CPRD
23	22	21	20	19	18	17	16
CPRD
15	14	13	12	11	10	9	8
CPRD
7	6	5	4	3	2	1	0
CPRD

• CPRD: Channel Period

-

PWM PWM Channel Counter Register (ch_num = 3)

Name: PWM_CCNT3

Access: read-only

Address: 0xFFFCC26C

31	30	29	28	27	26	25	24
CNT
23	22	21	20	19	18	17	16
CNT
15	14	13	12	11	10	9	8
CNT
7	6	5	4	3	2	1	0
CNT

• CNT: Channel Counter Register

-

PWM PWM Channel Update Register (ch_num = 3)

Name: PWM_CUPD3

Access: write-only

Address: 0xFFFCC270

31	30	29	28	27	26	25	24
CUPD
23	22	21	20	19	18	17	16
CUPD
15	14	13	12	11	10	9	8
CUPD
7	6	5	4	3	2	1	0
CUPD

• CUPD

-