AT91SAM7L128 SPI

Serial Peripheral Interface (SPI) User Interface

Registers

Register Mapping
Address	Register	Name	Access	Reset
0xFFFE0000	Control Register	SPI_CR	write-only	-
0xFFFE0004	Mode Register	SPI_MR	read-write	0x0
0xFFFE0008	Receive Data Register	SPI_RDR	read-only	0x0
0xFFFE000C	Transmit Data Register	SPI_TDR	write-only	-
0xFFFE0010	Status Register	SPI_SR	read-only	0x000000F0
0xFFFE0014	Interrupt Enable Register	SPI_IER	write-only	-
0xFFFE0018	Interrupt Disable Register	SPI_IDR	write-only	-
0xFFFE001C	Interrupt Mask Register	SPI_IMR	read-only	0x0
0xFFFE0030	Chip Select Register	SPI_CSR[4]	read-write	0x0
0xFFFE0100	Receive Pointer Register	SPI_RPR	read-write	0x0
0xFFFE0104	Receive Counter Register	SPI_RCR	read-write	0x0
0xFFFE0108	Transmit Pointer Register	SPI_TPR	read-write	0x0
0xFFFE010C	Transmit Counter Register	SPI_TCR	read-write	0x0
0xFFFE0110	Receive Next Pointer Register	SPI_RNPR	read-write	0x0
0xFFFE0114	Receive Next Counter Register	SPI_RNCR	read-write	0x0
0xFFFE0118	Transmit Next Pointer Register	SPI_TNPR	read-write	0x0
0xFFFE011C	Transmit Next Counter Register	SPI_TNCR	read-write	0x0
0xFFFE0120	PDC Transfer Control Register	SPI_PTCR	write-only	-
0xFFFE0124	PDC Transfer Status Register	SPI_PTSR	read-only	0x0

Register Fields

SPI Control Register

Name: SPI_CR

Access: write-only

Address: 0xFFFE0000

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	LASTXFER
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
SWRST	-	-	-	-	-	SPIDIS	SPIEN

SPIEN: SPI Enable

0 = No effect.
1 = Enables the SPI to transfer and receive data.

SPIDIS: SPI Disable

0 = No effect.
1 = Disables the SPI.

SWRST: SPI Software Reset

0 = No effect.
1 = Reset the SPI. A software-triggered hardware reset of the SPI interface is performed.

LASTXFER: Last Transfer

0 = No effect.
1 = The current NPCS will be deasserted after the character written in TD has been transferred. When CSAAT is set, this allows to close the communication with the current serial peripheral by raising the corresponding NPCS line as soon as TD transfer has completed.

SPI Mode Register

Name: SPI_MR

Access: read-write

Address: 0xFFFE0004

31	30	29	28	27	26	25	24
DLYBCS
23	22	21	20	19	18	17	16
-	-	-	-	PCS
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
LLB	-	-	MODFDIS	-	PCSDEC	PS	MSTR

MSTR: Master/Slave Mode

0 = SPI is in Slave mode.
1 = SPI is in Master mode.

PS: Peripheral Select

0 = Fixed Peripheral Select.
1 = Variable Peripheral Select.

PCSDEC: Chip Select Decode

0 = The chip selects are directly connected to a peripheral device.
1 = The four chip select lines are connected to a 4- to 16-bit decoder.

MODFDIS: Mode Fault Detection

0 = Mode fault detection is enabled.
1 = Mode fault detection is disabled.

LLB: Local Loopback Enable

0 = Local loopback path disabled.
1 = Local loopback path enabled (

PCS: Peripheral Chip Select

DLYBCS: Delay Between Chip Selects

SPI Receive Data Register

Name: SPI_RDR

Access: read-only

Address: 0xFFFE0008

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	PCS
15	14	13	12	11	10	9	8
RD
7	6	5	4	3	2	1	0
RD

RD: Receive Data

PCS: Peripheral Chip Select

SPI Transmit Data Register

Name: SPI_TDR

Access: write-only

Address: 0xFFFE000C

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	LASTXFER
23	22	21	20	19	18	17	16
-	-	-	-	PCS
15	14	13	12	11	10	9	8
TD
7	6	5	4	3	2	1	0
TD

TD: Transmit Data

PCS: Peripheral Chip Select

LASTXFER: Last Transfer

0 = No effect.
1 = The current NPCS will be deasserted after the character written in TD has been transferred. When CSAAT is set, this allows to close the communication with the current serial peripheral by raising the corresponding NPCS line as soon as TD transfer has completed.

SPI Status Register

Name: SPI_SR

Access: read-only

Address: 0xFFFE0010

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	SPIENS
15	14	13	12	11	10	9	8
-	-	-	-	-	-	TXEMPTY	NSSR
7	6	5	4	3	2	1	0
TXBUFE	RXBUFF	ENDTX	ENDRX	OVRES	MODF	TDRE	RDRF

RDRF: Receive Data Register Full

0 = No data has been received since the last read of SPI_RDR
1 = Data has been received and the received data has been transferred from the serializer to SPI_RDR since the last read of SPI_RDR.

TDRE: Transmit Data Register Empty

0 = Data has been written to SPI_TDR and not yet transferred to the serializer.
1 = The last data written in the Transmit Data Register has been transferred to the serializer.

MODF: Mode Fault Error

0 = No Mode Fault has been detected since the last read of SPI_SR.
1 = A Mode Fault occurred since the last read of the SPI_SR.

OVRES: Overrun Error Status

0 = No overrun has been detected since the last read of SPI_SR.
1 = An overrun has occurred since the last read of SPI_SR.

ENDRX: End of RX buffer

0 = The Receive Counter Register has not reached 0 since the last write in SPI_RCR(1) or SPI_RNCR(1).
1 = The Receive Counter Register has reached 0 since the last write in SPI_RCR(1) or SPI_RNCR(1).

ENDTX: End of TX buffer

0 = The Transmit Counter Register has not reached 0 since the last write in SPI_TCR(1) or SPI_TNCR(1).
1 = The Transmit Counter Register has reached 0 since the last write in SPI_TCR(1) or SPI_TNCR(1).

RXBUFF: RX Buffer Full

0 = SPI_RCR(1) or SPI_RNCR(1) has a value other than 0.
1 = Both SPI_RCR(1) and SPI_RNCR(1) have a value of 0.

TXBUFE: TX Buffer Empty

0 = SPI_TCR(1) or SPI_TNCR(1) has a value other than 0.
1 = Both SPI_TCR(1) and SPI_TNCR(1) have a value of 0.

NSSR: NSS Rising

0 = No rising edge detected on NSS pin since last read.
1 = A rising edge occurred on NSS pin since last read.

TXEMPTY: Transmission Registers Empty

0 = As soon as data is written in SPI_TDR.
1 = SPI_TDR and internal shifter are empty. If a transfer delay has been defined, TXEMPTY is set after the completion of such delay.

SPIENS: SPI Enable Status

0 = SPI is disabled.
1 = SPI is enabled.

SPI Interrupt Enable Register

Name: SPI_IER

Access: write-only

Address: 0xFFFE0014

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	TXEMPTY	NSSR
7	6	5	4	3	2	1	0
TXBUFE	RXBUFF	ENDTX	ENDRX	OVRES	MODF	TDRE	RDRF

RDRF: Receive Data Register Full Interrupt Enable

0 = No effect.
1 = Enables the corresponding interrupt.

TDRE: SPI Transmit Data Register Empty Interrupt Enable

0 = No effect.
1 = Enables the corresponding interrupt.

MODF: Mode Fault Error Interrupt Enable

0 = No effect.
1 = Enables the corresponding interrupt.

OVRES: Overrun Error Interrupt Enable

0 = No effect.
1 = Enables the corresponding interrupt.

ENDRX: End of Receive Buffer Interrupt Enable

0 = No effect.
1 = Enables the corresponding interrupt.

ENDTX: End of Transmit Buffer Interrupt Enable

0 = No effect.
1 = Enables the corresponding interrupt.

RXBUFF: Receive Buffer Full Interrupt Enable

0 = No effect.
1 = Enables the corresponding interrupt.

TXBUFE: Transmit Buffer Empty Interrupt Enable

0 = No effect.
1 = Enables the corresponding interrupt.

NSSR: NSS Rising Interrupt Enable

0 = No effect.
1 = Enables the corresponding interrupt.

TXEMPTY: Transmission Registers Empty Enable

SPI Interrupt Disable Register

Name: SPI_IDR

Access: write-only

Address: 0xFFFE0018

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	TXEMPTY	NSSR
7	6	5	4	3	2	1	0
TXBUFE	RXBUFF	ENDTX	ENDRX	OVRES	MODF	TDRE	RDRF

RDRF: Receive Data Register Full Interrupt Disable

0 = No effect.
1 = Disables the corresponding interrupt.

TDRE: SPI Transmit Data Register Empty Interrupt Disable

0 = No effect.
1 = Disables the corresponding interrupt.

MODF: Mode Fault Error Interrupt Disable

0 = No effect.
1 = Disables the corresponding interrupt.

OVRES: Overrun Error Interrupt Disable

0 = No effect.
1 = Disables the corresponding interrupt.

ENDRX: End of Receive Buffer Interrupt Disable

0 = No effect.
1 = Disables the corresponding interrupt.

ENDTX: End of Transmit Buffer Interrupt Disable

0 = No effect.
1 = Disables the corresponding interrupt.

RXBUFF: Receive Buffer Full Interrupt Disable

0 = No effect.
1 = Disables the corresponding interrupt.

TXBUFE: Transmit Buffer Empty Interrupt Disable

0 = No effect.
1 = Disables the corresponding interrupt.

NSSR: NSS Rising Interrupt Disable

0 = No effect.
1 = Disables the corresponding interrupt.

TXEMPTY: Transmission Registers Empty Disable

SPI Interrupt Mask Register

Name: SPI_IMR

Access: read-only

Address: 0xFFFE001C

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	TXEMPTY	NSSR
7	6	5	4	3	2	1	0
TXBUFE	RXBUFF	ENDTX	ENDRX	OVRES	MODF	TDRE	RDRF

RDRF: Receive Data Register Full Interrupt Mask

0 = The corresponding interrupt is not enabled.
1 = The corresponding interrupt is enabled.

TDRE: SPI Transmit Data Register Empty Interrupt Mask

0 = The corresponding interrupt is not enabled.
1 = The corresponding interrupt is enabled.

MODF: Mode Fault Error Interrupt Mask

0 = The corresponding interrupt is not enabled.
1 = The corresponding interrupt is enabled.

OVRES: Overrun Error Interrupt Mask

0 = The corresponding interrupt is not enabled.
1 = The corresponding interrupt is enabled.

ENDRX: End of Receive Buffer Interrupt Mask

0 = The corresponding interrupt is not enabled.
1 = The corresponding interrupt is enabled.

ENDTX: End of Transmit Buffer Interrupt Mask

0 = The corresponding interrupt is not enabled.
1 = The corresponding interrupt is enabled.

RXBUFF: Receive Buffer Full Interrupt Mask

0 = The corresponding interrupt is not enabled.
1 = The corresponding interrupt is enabled.

TXBUFE: Transmit Buffer Empty Interrupt Mask

0 = The corresponding interrupt is not enabled.
1 = The corresponding interrupt is enabled.

NSSR: NSS Rising Interrupt Mask

0 = The corresponding interrupt is not enabled.
1 = The corresponding interrupt is enabled.

TXEMPTY: Transmission Registers Empty Mask

SPI Chip Select Register

Name: SPI_CSR[0:3]

Access: read-write

Address: 0xFFFE0030

31	30	29	28	27	26	25	24
DLYBCT
23	22	21	20	19	18	17	16
DLYBS
15	14	13	12	11	10	9	8
SCBR
7	6	5	4	3	2	1	0
BITS				CSAAT	-	NCPHA	CPOL

CPOL: Clock Polarity

0 = The inactive state value of SPCK is logic level zero.
1 = The inactive state value of SPCK is logic level one.

NCPHA: Clock Phase

0 = Data is changed on the leading edge of SPCK and captured on the following edge of SPCK.
1 = Data is captured on the leading edge of SPCK and changed on the following edge of SPCK.

CSAAT: Chip Select Active After Transfer

0 = The Peripheral Chip Select Line rises as soon as the last transfer is achieved.
1 = The Peripheral Chip Select does not rise after the last transfer is achieved. It remains active until a new transfer is requested on a different chip select.

BITS: Bits Per Transfer

0x0 = 8
0x1 = 9
0x2 = 10
0x3 = 11
0x4 = 12
0x5 = 13
0x6 = 14
0x7 = 15
0x8 = 16
0x9 = Reserved
0xA = Reserved
0xB = Reserved
0xC = Reserved
0xD = Reserved
0xE = Reserved
0xF = Reserved

SCBR: Serial Clock Baud Rate

DLYBS: Delay Before SPCK

DLYBCT: Delay Between Consecutive Transfers

SPI Receive Pointer Register

Name: SPI_RPR

Access: read-write

Address: 0xFFFE0100

31	30	29	28	27	26	25	24
RXPTR
23	22	21	20	19	18	17	16
RXPTR
15	14	13	12	11	10	9	8
RXPTR
7	6	5	4	3	2	1	0
RXPTR

RXPTR: Receive Pointer Address

SPI Receive Counter Register

Name: SPI_RCR

Access: read-write

Address: 0xFFFE0104

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
RXCTR
7	6	5	4	3	2	1	0
RXCTR

RXCTR: Receive Counter Value

SPI Transmit Pointer Register

Name: SPI_TPR

Access: read-write

Address: 0xFFFE0108

31	30	29	28	27	26	25	24
TXPTR
23	22	21	20	19	18	17	16
TXPTR
15	14	13	12	11	10	9	8
TXPTR
7	6	5	4	3	2	1	0
TXPTR

TXPTR: Transmit Pointer Address

SPI Transmit Counter Register

Name: SPI_TCR

Access: read-write

Address: 0xFFFE010C

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
TXCTR
7	6	5	4	3	2	1	0
TXCTR

TXCTR: Transmit Counter Value

SPI Receive Next Pointer Register

Name: SPI_RNPR

Access: read-write

Address: 0xFFFE0110

31	30	29	28	27	26	25	24
RXNPTR
23	22	21	20	19	18	17	16
RXNPTR
15	14	13	12	11	10	9	8
RXNPTR
7	6	5	4	3	2	1	0
RXNPTR

RXNPTR: Receive Next Pointer Address

SPI Receive Next Counter Register

Name: SPI_RNCR

Access: read-write

Address: 0xFFFE0114

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
RXNCR
7	6	5	4	3	2	1	0
RXNCR

RXNCR: Receive Next Counter Value

SPI Transmit Next Pointer Register

Name: SPI_TNPR

Access: read-write

Address: 0xFFFE0118

31	30	29	28	27	26	25	24
TXNPTR
23	22	21	20	19	18	17	16
TXNPTR
15	14	13	12	11	10	9	8
TXNPTR
7	6	5	4	3	2	1	0
TXNPTR

TXNPTR: Transmit Next Pointer Address

SPI Transmit Next Counter Register

Name: SPI_TNCR

Access: read-write

Address: 0xFFFE011C

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
TXNCR
7	6	5	4	3	2	1	0
TXNCR

TXNCR: Transmit Next Counter Value

SPI PDC Transfer Control Register

Name: SPI_PTCR

Access: write-only

Address: 0xFFFE0120

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	TXTDIS	TXTEN
7	6	5	4	3	2	1	0
-	-	-	-	-	-	RXTDIS	RXTEN

RXTEN: Receiver Transfer Enable

0 = No effect.
1 = Enables the receiver PDC transfer requests if RXTDIS is not set.

RXTDIS: Receiver Transfer Disable

0 = No effect.
1 = Disables the receiver PDC transfer requests.

TXTEN: Transmitter Transfer Enable

0 = No effect.
1 = Enables the transmitter PDC transfer requests.

TXTDIS: Transmitter Transfer Disable

0 = No effect.
1 = Disables the transmitter PDC transfer requests.

SPI PDC Transfer Status Register

Name: SPI_PTSR

Access: read-only

Address: 0xFFFE0124

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	TXTEN
7	6	5	4	3	2	1	0
-	-	-	-	-	-	-	RXTEN

RXTEN: Receiver Transfer Enable

0 = Receiver PDC transfer requests are disabled.
1 = Receiver PDC transfer requests are enabled.

TXTEN: Transmitter Transfer Enable

0 = Transmitter PDC transfer requests are disabled.
1 = Transmitter PDC transfer requests are enabled.

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	PCS
15	14	13	12	11	10	9	8
RD
7	6	5	4	3	2	1	0
RD

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	PCS
15	14	13	12	11	10	9	8
RD
7	6	5	4	3	2	1	0
RD

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	PCS
15	14	13	12	11	10	9	8
RD
7	6	5	4	3	2	1	0
RD