AT91SAM7L128 TWI

Two-wire Interface (TWI) User Interface

Registers

Register Mapping

Address	Register	Name	Access	Reset
0xFFFB8000	Control Register	TWI_CR	write-only	-
0xFFFB8004	Master Mode Register	TWI_MMR	read-write	0x00000000
0xFFFB8008	Slave Mode Register	TWI_SMR	read-write	0x00000000
0xFFFB800C	Internal Address Register	TWI_IADR	read-write	0x00000000
0xFFFB8010	Clock Waveform Generator Register	TWI_CWGR	read-write	0x00000000
0xFFFB8020	Status Register	TWI_SR	read-only	0x0000F009
0xFFFB8024	Interrupt Enable Register	TWI_IER	write-only	-
0xFFFB8028	Interrupt Disable Register	TWI_IDR	write-only	-
0xFFFB802C	Interrupt Mask Register	TWI_IMR	read-only	0x00000000
0xFFFB8030	Receive Holding Register	TWI_RHR	read-only	0x00000000
0xFFFB8034	Transmit Holding Register	TWI_THR	write-only	0x00000000
0xFFFB8100	Receive Pointer Register	TWI_RPR	read-write	0x0
0xFFFB8104	Receive Counter Register	TWI_RCR	read-write	0x0
0xFFFB8108	Transmit Pointer Register	TWI_TPR	read-write	0x0
0xFFFB810C	Transmit Counter Register	TWI_TCR	read-write	0x0
0xFFFB8110	Receive Next Pointer Register	TWI_RNPR	read-write	0x0
0xFFFB8114	Receive Next Counter Register	TWI_RNCR	read-write	0x0
0xFFFB8118	Transmit Next Pointer Register	TWI_TNPR	read-write	0x0
0xFFFB811C	Transmit Next Counter Register	TWI_TNCR	read-write	0x0
0xFFFB8120	PDC Transfer Control Register	TWI_PTCR	write-only	-
0xFFFB8124	PDC Transfer Status Register	TWI_PTSR	read-only	0x0

Register Fields

TWI Control Register

Name: TWI_CR

Access: write-only

Address: 0xFFFB8000

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
SWRST	-	SVDIS	SVEN	MSDIS	MSEN	STOP	START

• START: Send a START Condition
• 0 = No effect.
• 1 = A frame beginning with a START bit is transmitted according to the features defined in the mode register.
• STOP: Send a STOP Condition
• 0 = No effect.
• 1 = STOP Condition is sent just after completing the current byte transmission in master read mode.
• MSEN: TWI Master Mode Enabled
• 0 = No effect.
• 1 = If MSDIS = 0, the master mode is enabled.
• MSDIS: TWI Master Mode Disabled
• 0 = No effect.
• 1 = The master mode is disabled, all pending data is transmitted. The shifter and holding characters (if it contains data) are transmitted in case of write operation. In read operation, the character being transferred must be completely received before disabling.
• SVEN: TWI Slave Mode Enabled
• 0 = No effect.
• 1 = If SVDIS = 0, the slave mode is enabled.
• SVDIS: TWI Slave Mode Disabled
• 0 = No effect.
• 1 = The slave mode is disabled. The shifter and holding characters (if it contains data) are transmitted in case of read oper- ation. In write operation, the character being transferred must be completely received before disabling.
• SWRST: Software Reset
• 0 = No effect.
• 1 = Equivalent to a system reset.

TWI Master Mode Register

Name: TWI_MMR

Access: read-write

Address: 0xFFFB8004

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	DADR
15	14	13	12	11	10	9	8
-	-	-	MREAD	-	-	IADRSZ
7	6	5	4	3	2	1	0
-	-	-	-	-	-	-	-

• IADRSZ: Internal Device Address Size
• 0x0 = No internal device address
• 0x1 = One-byte internal device address
• 0x2 = Two-byte internal device address
• 0x3 = Three-byte internal device address
• MREAD: Master Read Direction
• 0 = Master write direction.
• 1 = Master read direction.
• DADR: Device Address

-

TWI Slave Mode Register

Name: TWI_SMR

Access: read-write

Address: 0xFFFB8008

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	SADR
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
-	-	-	-	-	-	-	-

• SADR: Slave Address

-

TWI Internal Address Register

Name: TWI_IADR

Access: read-write

Address: 0xFFFB800C

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
IADR
15	14	13	12	11	10	9	8
IADR
7	6	5	4	3	2	1	0
IADR

• IADR: Internal Address

-

TWI Clock Waveform Generator Register

Name: TWI_CWGR

Access: read-write

Address: 0xFFFB8010

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	CKDIV
15	14	13	12	11	10	9	8
CHDIV
7	6	5	4	3	2	1	0
CLDIV

• CLDIV: Clock Low Divider

-

• CHDIV: Clock High Divider

-

• CKDIV: Clock Divider

-

TWI Status Register

Name: TWI_SR

Access: read-only

Address: 0xFFFB8020

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
TXBUFE	RXBUFF	ENDTX	ENDRX	EOSACC	SCLWS	ARBLST	NACK
7	6	5	4	3	2	1	0
-	OVRE	GACC	SVACC	SVREAD	TXRDY	RXRDY	TXCOMP

• TXCOMP: Transmission Completed (automatically set / reset)

-

• RXRDY: Receive Holding Register Ready (automatically set / reset)
• 0 = No character has been received since the last TWI_RHR read operation.
• 1 = A byte has been received in the TWI_RHR since the last read.
• TXRDY: Transmit Holding Register Ready (automatically set / reset)

-

• SVREAD: Slave Read (automatically set / reset)
• 0 = Indicates that a write access is performed by a Master.
• 1 = Indicates that a read access is performed by a Master.
• SVACC: Slave Access (automatically set / reset)
• 0 = TWI is not addressed. SVACC is automatically cleared after a NACK or a STOP condition is detected.
• 1 = Indicates that the address decoding sequence has matched (A Master has sent SADR). SVACC remains high until a NACK or a STOP condition is detected.
• GACC: General Call Access (clear on read)
• 0 = No General Call has been detected.
• 1 = A General Call has been detected. After the detection of General Call, the programmer decoded the commands that fol- low and the programming sequence.
• OVRE: Overrun Error (clear on read)
• 0 = TWI_RHR has not been loaded while RXRDY was set
• 1 = TWI_RHR has been loaded while RXRDY was set. Reset by read in TWI_SR when TXCOMP is set.
• NACK: Not Acknowledged (clear on read)

-

• ARBLST: Arbitration Lost (clear on read)
• 0 = Arbitration won.
• 1 = Arbitration lost. Another master of the TWI bus has won the multi-master arbitration. TXCOMP is set at the same time.
• SCLWS: Clock Wait State (automatically set / reset)
• 0 = The clock is not stretched.
• 1 = The clock is stretched. TWI_THR / TWI_RHR buffer is not filled / emptied before the emission / reception of a new character.
• EOSACC: End Of Slave Access (clear on read)
• 0 = A slave access is being performing.
• 1 = The Slave Access is finished. End Of Slave Access is automatically set as soon as SVACC is reset.
• ENDRX: End of RX buffer
• 0 = The Receive Counter Register has not reached 0 since the last write in TWI_RCR or TWI_RNCR.
• 1 = The Receive Counter Register has reached 0 since the last write in TWI_RCR or TWI_RNCR.
• ENDTX: End of TX buffer
• 0 = The Transmit Counter Register has not reached 0 since the last write in TWI_TCR or TWI_TNCR.
• 1 = The Transmit Counter Register has reached 0 since the last write in TWI_TCR or TWI_TNCR.
• RXBUFF: RX Buffer Full
• 0 = TWI_RCR or TWI_RNCR have a value other than 0.
• 1 = Both TWI_RCR and TWI_RNCR have a value of 0.
• TXBUFE: TX Buffer Empty
• 0 = TWI_TCR or TWI_TNCR have a value other than 0.
• 1 = Both TWI_TCR and TWI_TNCR have a value of 0.

TWI Interrupt Enable Register

Name: TWI_IER

Access: write-only

Address: 0xFFFB8024

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
TXBUFE	RXBUFF	ENDTX	ENDRX	EOSACC	SCL_WS	ARBLST	NACK
7	6	5	4	3	2	1	0
-	OVRE	GACC	SVACC	-	TXRDY	RXRDY	TXCOMP

• TXCOMP: Transmission Completed Interrupt Enable
• 0 = No effect.
• 1 = Enables the corresponding interrupt.
• RXRDY: Receive Holding Register Ready Interrupt Enable
• 0 = No effect.
• 1 = Enables the corresponding interrupt.
• TXRDY: Transmit Holding Register Ready Interrupt Enable
• 0 = No effect.
• 1 = Enables the corresponding interrupt.
• SVACC: Slave Access Interrupt Enable
• 0 = No effect.
• 1 = Enables the corresponding interrupt.
• GACC: General Call Access Interrupt Enable
• 0 = No effect.
• 1 = Enables the corresponding interrupt.
• OVRE: Overrun Error Interrupt Enable
• 0 = No effect.
• 1 = Enables the corresponding interrupt.
• NACK: Not Acknowledge Interrupt Enable
• 0 = No effect.
• 1 = Enables the corresponding interrupt.
• ARBLST: Arbitration Lost Interrupt Enable
• 0 = No effect.
• 1 = Enables the corresponding interrupt.
• SCL_WS: Clock Wait State Interrupt Enable
• 0 = No effect.
• 1 = Enables the corresponding interrupt.
• EOSACC: End Of Slave Access Interrupt Enable
• 0 = No effect.
• 1 = Enables the corresponding interrupt.
• ENDRX: End of Receive Buffer Interrupt Enable
• 0 = No effect.
• 1 = Enables the corresponding interrupt.
• ENDTX: End of Transmit Buffer Interrupt Enable
• 0 = No effect.
• 1 = Enables the corresponding interrupt.
• RXBUFF: Receive Buffer Full Interrupt Enable
• 0 = No effect.
• 1 = Enables the corresponding interrupt.
• TXBUFE: Transmit Buffer Empty Interrupt Enable
• 0 = No effect.
• 1 = Enables the corresponding interrupt.

TWI Interrupt Disable Register

Name: TWI_IDR

Access: write-only

Address: 0xFFFB8028

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
TXBUFE	RXBUFF	ENDTX	ENDRX	EOSACC	SCL_WS	ARBLST	NACK
7	6	5	4	3	2	1	0
-	OVRE	GACC	SVACC	-	TXRDY	RXRDY	TXCOMP

• TXCOMP: Transmission Completed Interrupt Disable
• 0 = No effect.
• 1 = Disables the corresponding interrupt.
• RXRDY: Receive Holding Register Ready Interrupt Disable
• 0 = No effect.
• 1 = Disables the corresponding interrupt.
• TXRDY: Transmit Holding Register Ready Interrupt Disable
• 0 = No effect.
• 1 = Disables the corresponding interrupt.
• SVACC: Slave Access Interrupt Disable
• 0 = No effect.
• 1 = Disables the corresponding interrupt.
• GACC: General Call Access Interrupt Disable
• 0 = No effect.
• 1 = Disables the corresponding interrupt.
• OVRE: Overrun Error Interrupt Disable
• 0 = No effect.
• 1 = Disables the corresponding interrupt.
• NACK: Not Acknowledge Interrupt Disable
• 0 = No effect.
• 1 = Disables the corresponding interrupt.
• ARBLST: Arbitration Lost Interrupt Disable
• 0 = No effect.
• 1 = Disables the corresponding interrupt.
• SCL_WS: Clock Wait State Interrupt Disable
• 0 = No effect.
• 1 = Disables the corresponding interrupt.
• EOSACC: End Of Slave Access Interrupt Disable
• 0 = No effect.
• 1 = Disables the corresponding interrupt.
• ENDRX: End of Receive Buffer Interrupt Disable
• 0 = No effect.
• 1 = Disables the corresponding interrupt.
• ENDTX: End of Transmit Buffer Interrupt Disable
• 0 = No effect.
• 1 = Disables the corresponding interrupt.
• RXBUFF: Receive Buffer Full Interrupt Disable
• 0 = No effect.
• 1 = Disables the corresponding interrupt.
• TXBUFE: Transmit Buffer Empty Interrupt Disable
• 0 = No effect.
• 1 = Disables the corresponding interrupt.

TWI Interrupt Mask Register

Name: TWI_IMR

Access: read-only

Address: 0xFFFB802C

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
TXBUFE	RXBUFF	ENDTX	ENDRX	EOSACC	SCL_WS	ARBLST	NACK
7	6	5	4	3	2	1	0
-	OVRE	GACC	SVACC	-	TXRDY	RXRDY	TXCOMP

• TXCOMP: Transmission Completed Interrupt Mask
• 0 = The corresponding interrupt is disabled.
• 1 = The corresponding interrupt is enabled.
• RXRDY: Receive Holding Register Ready Interrupt Mask
• 0 = The corresponding interrupt is disabled.
• 1 = The corresponding interrupt is enabled.
• TXRDY: Transmit Holding Register Ready Interrupt Mask
• 0 = The corresponding interrupt is disabled.
• 1 = The corresponding interrupt is enabled.
• SVACC: Slave Access Interrupt Mask
• 0 = The corresponding interrupt is disabled.
• 1 = The corresponding interrupt is enabled.
• GACC: General Call Access Interrupt Mask
• 0 = The corresponding interrupt is disabled.
• 1 = The corresponding interrupt is enabled.
• OVRE: Overrun Error Interrupt Mask
• 0 = The corresponding interrupt is disabled.
• 1 = The corresponding interrupt is enabled.
• NACK: Not Acknowledge Interrupt Mask
• 0 = The corresponding interrupt is disabled.
• 1 = The corresponding interrupt is enabled.
• ARBLST: Arbitration Lost Interrupt Mask
• 0 = The corresponding interrupt is disabled.
• 1 = The corresponding interrupt is enabled.
• SCL_WS: Clock Wait State Interrupt Mask
• 0 = The corresponding interrupt is disabled.
• 1 = The corresponding interrupt is enabled.
• EOSACC: End Of Slave Access Interrupt Mask
• 0 = The corresponding interrupt is disabled.
• 1 = The corresponding interrupt is enabled.
• ENDRX: End of Receive Buffer Interrupt Mask
• 0 = The corresponding interrupt is disabled.
• 1 = The corresponding interrupt is enabled.
• ENDTX: End of Transmit Buffer Interrupt Mask
• 0 = The corresponding interrupt is disabled.
• 1 = The corresponding interrupt is enabled.
• RXBUFF: Receive Buffer Full Interrupt Mask
• 0 = The corresponding interrupt is disabled.
• 1 = The corresponding interrupt is enabled.
• TXBUFE: Transmit Buffer Empty Interrupt Mask
• 0 = The corresponding interrupt is disabled.
• 1 = The corresponding interrupt is enabled.

TWI Receive Holding Register

Name: TWI_RHR

Access: read-only

Address: 0xFFFB8030

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
RXDATA

• RXDATA: Master or Slave Receive Holding Data

-

TWI Transmit Holding Register

Name: TWI_THR

Access: write-only

Address: 0xFFFB8034

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
TXDATA

• TXDATA: Master or Slave Transmit Holding Data

-

TWI Receive Pointer Register

Name: TWI_RPR

Access: read-write

Address: 0xFFFB8100

31	30	29	28	27	26	25	24
RXPTR
23	22	21	20	19	18	17	16
RXPTR
15	14	13	12	11	10	9	8
RXPTR
7	6	5	4	3	2	1	0
RXPTR

• RXPTR: Receive Pointer Address

-

TWI Receive Counter Register

Name: TWI_RCR

Access: read-write

Address: 0xFFFB8104

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
RXCTR
7	6	5	4	3	2	1	0
RXCTR

• RXCTR: Receive Counter Value

-

TWI Transmit Pointer Register

Name: TWI_TPR

Access: read-write

Address: 0xFFFB8108

31	30	29	28	27	26	25	24
TXPTR
23	22	21	20	19	18	17	16
TXPTR
15	14	13	12	11	10	9	8
TXPTR
7	6	5	4	3	2	1	0
TXPTR

• TXPTR: Transmit Pointer Address

-

TWI Transmit Counter Register

Name: TWI_TCR

Access: read-write

Address: 0xFFFB810C

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
TXCTR
7	6	5	4	3	2	1	0
TXCTR

• TXCTR: Transmit Counter Value

-

TWI Receive Next Pointer Register

Name: TWI_RNPR

Access: read-write

Address: 0xFFFB8110

31	30	29	28	27	26	25	24
RXNPTR
23	22	21	20	19	18	17	16
RXNPTR
15	14	13	12	11	10	9	8
RXNPTR
7	6	5	4	3	2	1	0
RXNPTR

• RXNPTR: Receive Next Pointer Address

-

TWI Receive Next Counter Register

Name: TWI_RNCR

Access: read-write

Address: 0xFFFB8114

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
RXNCR
7	6	5	4	3	2	1	0
RXNCR

• RXNCR: Receive Next Counter Value

-

TWI Transmit Next Pointer Register

Name: TWI_TNPR

Access: read-write

Address: 0xFFFB8118

31	30	29	28	27	26	25	24
TXNPTR
23	22	21	20	19	18	17	16
TXNPTR
15	14	13	12	11	10	9	8
TXNPTR
7	6	5	4	3	2	1	0
TXNPTR

• TXNPTR: Transmit Next Pointer Address

-

TWI Transmit Next Counter Register

Name: TWI_TNCR

Access: read-write

Address: 0xFFFB811C

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
TXNCR
7	6	5	4	3	2	1	0
TXNCR

• TXNCR: Transmit Next Counter Value

-

TWI PDC Transfer Control Register

Name: TWI_PTCR

Access: write-only

Address: 0xFFFB8120

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	TXTDIS	TXTEN
7	6	5	4	3	2	1	0
-	-	-	-	-	-	RXTDIS	RXTEN

• RXTEN: Receiver Transfer Enable
• 0 = No effect.
• 1 = Enables the receiver PDC transfer requests if RXTDIS is not set.
• RXTDIS: Receiver Transfer Disable
• 0 = No effect.
• 1 = Disables the receiver PDC transfer requests.
• TXTEN: Transmitter Transfer Enable
• 0 = No effect.
• 1 = Enables the transmitter PDC transfer requests.
• TXTDIS: Transmitter Transfer Disable
• 0 = No effect.
• 1 = Disables the transmitter PDC transfer requests.

TWI PDC Transfer Status Register

Name: TWI_PTSR

Access: read-only

Address: 0xFFFB8124

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	TXTEN
7	6	5	4	3	2	1	0
-	-	-	-	-	-	-	RXTEN

• RXTEN: Receiver Transfer Enable
• 0 = Receiver PDC transfer requests are disabled.
• 1 = Receiver PDC transfer requests are enabled.
• TXTEN: Transmitter Transfer Enable
• 0 = Transmitter PDC transfer requests are disabled.
• 1 = Transmitter PDC transfer requests are enabled.