AT91SAM7L128 USART1

Universal Synchronous Asynchronous Receiver Transmitter (USART1) User Interface

Registers

Register Mapping

Address	Register	Name	Access	Reset
0xFFFC4000	Control Register	USART1_CR	write-only	-
0xFFFC4004	Mode Register	USART1_MR	read-write	-
0xFFFC4008	Interrupt Enable Register	USART1_IER	write-only	-
0xFFFC400C	Interrupt Disable Register	USART1_IDR	write-only	-
0xFFFC4010	Interrupt Mask Register	USART1_IMR	read-only	0x0
0xFFFC4014	Channel Status Register	USART1_CSR	read-only	-
0xFFFC4018	Receiver Holding Register	USART1_RHR	read-only	0x0
0xFFFC401C	Transmitter Holding Register	USART1_THR	write-only	-
0xFFFC4020	Baud Rate Generator Register	USART1_BRGR	read-write	0x0
0xFFFC4024	Receiver Time-out Register	USART1_RTOR	read-write	0x0
0xFFFC4028	Transmitter Timeguard Register	USART1_TTGR	read-write	0x0
0xFFFC4040	FI DI Ratio Register	USART1_FIDI	read-write	0x174
0xFFFC4044	Number of Errors Register	USART1_NER	read-only	-
0xFFFC404C	IrDA Filter Register	USART1_IF	read-write	0x0
0xFFFC4050	Manchester Encoder Decoder Register	USART1_MAN	read-write	0x30011004
0xFFFC40FC	Version Register	USART1_VERSION	read-only	-
0xFFFC4100	Receive Pointer Register	USART1_RPR	read-write	0x0
0xFFFC4104	Receive Counter Register	USART1_RCR	read-write	0x0
0xFFFC4108	Transmit Pointer Register	USART1_TPR	read-write	0x0
0xFFFC410C	Transmit Counter Register	USART1_TCR	read-write	0x0
0xFFFC4110	Receive Next Pointer Register	USART1_RNPR	read-write	0x0
0xFFFC4114	Receive Next Counter Register	USART1_RNCR	read-write	0x0
0xFFFC4118	Transmit Next Pointer Register	USART1_TNPR	read-write	0x0
0xFFFC411C	Transmit Next Counter Register	USART1_TNCR	read-write	0x0
0xFFFC4120	PDC Transfer Control Register	USART1_PTCR	write-only	-
0xFFFC4124	PDC Transfer Status Register	USART1_PTSR	read-only	0x0

Register Fields

USART1 Control Register

Name: USART1_CR

Access: write-only

Address: 0xFFFC4000

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	RTSDIS	RTSEN	DTRDIS	DTREN
15	14	13	12	11	10	9	8
RETTO	RSTNACK	RSTIT	SENDA	STTTO	STPBRK	STTBRK	RSTSTA
7	6	5	4	3	2	1	0
TXDIS	TXEN	RXDIS	RXEN	RSTTX	RSTRX	-	-

• RSTRX: Reset Receiver
• 0 = No effect.
• 1 = Resets the receiver.
• RSTTX: Reset Transmitter
• 0 = No effect.
• 1 = Resets the transmitter.
• RXEN: Receiver Enable
• 0 = No effect.
• 1 = Enables the receiver, if RXDIS is 0.
• RXDIS: Receiver Disable
• 0 = No effect.
• 1 = Disables the receiver.
• TXEN: Transmitter Enable
• 0 = No effect.
• 1 = Enables the transmitter if TXDIS is 0.
• TXDIS: Transmitter Disable
• 0 = No effect.
• 1 = Disables the transmitter.
• RSTSTA: Reset Status Bits
• 0 = No effect.
• 1 = Resets the status bits PARE, FRAME, OVRE, MANERR and RXBRK in US_CSR.
• STTBRK: Start Break
• 0 = No effect.
• 1 = Starts transmission of a break after the characters present in US_THR and the Transmit Shift Register have been trans- mitted. No effect if a break is already being transmitted.
• STPBRK: Stop Break
• 0 = No effect.
• 1 = Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods. No effect if no break is being transmitted.
• STTTO: Start Time-out
• 0 = No effect.
• 1 = Starts waiting for a character before clocking the time-out counter. Resets the status bit TIMEOUT in US_CSR.
• SENDA: Send Address
• 0 = No effect.
• 1 = In Multidrop Mode only, the next character written to the US_THR is sent with the address bit set.
• RSTIT: Reset Iterations
• 0 = No effect.
• 1 = Resets ITERATION in US_CSR. No effect if the ISO7816 is not enabled.
• RSTNACK: Reset Non Acknowledge
• 0 = No effect
• 1 = Resets NACK in US_CSR.
• RETTO: Rearm Time-out
• 0 = No effect
• 1 = Restart Time-out
• DTREN: Data Terminal Ready Enable
• 0 = No effect.
• 1 = Drives the pin DTR at 0.
• DTRDIS: Data Terminal Ready Disable
• 0 = No effect.
• 1 = Drives the pin DTR to 1.
• RTSEN: Request to Send Enable
• 0 = No effect.
• 1 = Drives the pin RTS to 0.
• RTSDIS: Request to Send Disable
• 0 = No effect.
• 1 = Drives the pin RTS to 1.

USART1 Mode Register

Name: USART1_MR

Access: read-write

Address: 0xFFFC4004

31	30	29	28	27	26	25	24
ONEBIT	MODSYNC_	MAN	FILTER	-	MAX_ITERATION
23	22	21	20	19	18	17	16
-	VAR_SYNC	DSNACK	INACK	OVER	CLKO	MODE9	MSBF
15	14	13	12	11	10	9	8
CHMODE		NBSTOP		PAR			SYNC
7	6	5	4	3	2	1	0
CHRL		USCLKS		USART_MODE

• USART_MODE
• 0x0 = Normal
• 0x1 = RS485
• 0x2 = Hardware Handshaking
• 0x3 = Modem
• 0x4 = IS07816 Protocol: T = 0
• 0x6 = IS07816 Protocol: T = 1
• 0x8 = IrDA
• USCLKS: Clock Selection
• 0x0 = MCK
• 0x1 = MCK/DIV (DIV = 8)
• 0x2 = Reserved
• 0x3 = SCK
• CHRL: Character Length.
• 0x0 = 5 bits
• 0x1 = 6 bits
• 0x2 = 7 bits
• 0x3 = 8 bits
• SYNC: Synchronous Mode Select
• 0 = USART operates in Asynchronous Mode.
• 1 = USART operates in Synchronous Mode.
• PAR: Parity Type
• 0x0 = Even parity
• 0x1 = Odd parity
• 0x2 = Parity forced to 0 (Space)
• 0x3 = Parity forced to 1 (Mark)
• NBSTOP: Number of Stop Bits

-

• CHMODE: Channel Mode
• 0x0 = Normal Mode
• 0x1 = Automatic Echo. Receiver input is connected to the TXD pin.
• 0x2 = Local Loopback. Transmitter output is connected to the Receiver Input..
• 0x3 = Remote Loopback. RXD pin is internally connected to the TXD pin.
• MSBF: Bit Order
• 0 = Least Significant Bit is sent/received first.
• 1 = Most Significant Bit is sent/received first.
• MODE9: 9-bit Character Length
• 0 = CHRL defines character length.
• 1 = 9-bit character length.
• CLKO: Clock Output Select
• 0 = The USART does not drive the SCK pin.
• 1 = The USART drives the SCK pin if USCLKS does not select the external clock SCK.
• OVER: Oversampling Mode
• 0 = 16x Oversampling.
• 1 = 8x Oversampling.
• INACK: Inhibit Non Acknowledge
• 0 = The NACK is generated.
• 1 = The NACK is not generated.
• DSNACK: Disable Successive NACK
• 0 = NACK is sent on the ISO line as soon as a parity error occurs in the received character (unless INACK is set).
• 1 = Successive parity errors are counted up to the value specified in the MAX_ITERATION field. These parity errors gener- ate a NACK on the ISO line. As soon as this value is reached, no additional NACK is sent on the ISO line. The flag ITERATION is asserted.
• VAR_SYNC: Variable Synchronization of Command/Data Sync Start Frame Delimiter
• 0 = User defined configuration of command or data sync field depending on SYNC value.
• 1 = The sync field is updated when a character is written into US_THR register.
• MAX_ITERATION

-

• FILTER: Infrared Receive Line Filter
• 0 = The USART does not filter the receive line.
• 1 = The USART filters the receive line using a three-sample filter (1/16-bit clock) (2 over 3 majority).
• MAN: Manchester Encoder/Decoder Enable
• 0 = Manchester Encoder/Decoder are disabled.
• 1 = Manchester Encoder/Decoder are enabled.
• MODSYNC_

-

• ONEBIT: Start Frame Delimiter Selector
• 0 = Start Frame delimiter is COMMAND or DATA SYNC.
• 1 = Start Frame delimiter is One Bit.

USART1 Interrupt Enable Register

Name: USART1_IER

Access: write-only

Address: 0xFFFC4008

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	_
23	22	21	20	19	18	17	16
-	-	-	MANE	CTSIC	DCDIC	DSRIC	RIIC
15	14	13	12	11	10	9	8
-	-	NACK	RXBUFF	TXBUFE	ITER	TXEMPTY	TIMEOUT
7	6	5	4	3	2	1	0
PARE	FRAME	OVRE	ENDTX	ENDRX	RXBRK	TXRDY	RXRDY

• RXRDY: RXRDY Interrupt Enable

-

• TXRDY: TXRDY Interrupt Enable

-

• RXBRK: Receiver Break Interrupt Enable

-

• ENDRX: End of Receive Transfer Interrupt Enable

-

• ENDTX: End of Transmit Interrupt Enable

-

• OVRE: Overrun Error Interrupt Enable

-

• FRAME: Framing Error Interrupt Enable

-

• PARE: Parity Error Interrupt Enable

-

• TIMEOUT: Time-out Interrupt Enable

-

• TXEMPTY: TXEMPTY Interrupt Enable

-

• ITER: Iteration Interrupt Enable

-

• TXBUFE: Buffer Empty Interrupt Enable

-

• RXBUFF: Buffer Full Interrupt Enable

-

• NACK: Non Acknowledge Interrupt Enable

-

• RIIC: Ring Indicator Input Change Enable

-

• DSRIC: Data Set Ready Input Change Enable

-

• DCDIC: Data Carrier Detect Input Change Interrupt Enable

-

• CTSIC: Clear to Send Input Change Interrupt Enable

-

• MANE: Manchester Error Interrupt Enable

-

• _

-

USART1 Interrupt Disable Register

Name: USART1_IDR

Access: write-only

Address: 0xFFFC400C

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	_
23	22	21	20	19	18	17	16
-	-	-	MANE	CTSIC	DCDIC	DSRIC	RIIC
15	14	13	12	11	10	9	8
-	-	NACK	RXBUFF	TXBUFE	ITER	TXEMPTY	TIMEOUT
7	6	5	4	3	2	1	0
PARE	FRAME	OVRE	ENDTX	ENDRX	RXBRK	TXRDY	RXRDY

• RXRDY: RXRDY Interrupt Disable

-

• TXRDY: TXRDY Interrupt Disable

-

• RXBRK: Receiver Break Interrupt Disable

-

• ENDRX: End of Receive Transfer Interrupt Disable

-

• ENDTX: End of Transmit Interrupt Disable

-

• OVRE: Overrun Error Interrupt Disable

-

• FRAME: Framing Error Interrupt Disable

-

• PARE: Parity Error Interrupt Disable

-

• TIMEOUT: Time-out Interrupt Disable

-

• TXEMPTY: TXEMPTY Interrupt Disable

-

• ITER: Iteration Interrupt Enable

-

• TXBUFE: Buffer Empty Interrupt Disable

-

• RXBUFF: Buffer Full Interrupt Disable

-

• NACK: Non Acknowledge Interrupt Disable

-

• RIIC: Ring Indicator Input Change Disable

-

• DSRIC: Data Set Ready Input Change Disable

-

• DCDIC: Data Carrier Detect Input Change Interrupt Disable

-

• CTSIC: Clear to Send Input Change Interrupt Disable

-

• MANE: Manchester Error Interrupt Disable

-

• _

-

USART1 Interrupt Mask Register

Name: USART1_IMR

Access: read-only

Address: 0xFFFC4010

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	_
23	22	21	20	19	18	17	16
-	-	-	MANE	CTSIC	DCDIC	DSRIC	RIIC
15	14	13	12	11	10	9	8
-	-	NACK	RXBUFF	TXBUFE	ITER	TXEMPTY	TIMEOUT
7	6	5	4	3	2	1	0
PARE	FRAME	OVRE	ENDTX	ENDRX	RXBRK	TXRDY	RXRDY

• RXRDY: RXRDY Interrupt Mask

-

• TXRDY: TXRDY Interrupt Mask

-

• RXBRK: Receiver Break Interrupt Mask

-

• ENDRX: End of Receive Transfer Interrupt Mask

-

• ENDTX: End of Transmit Interrupt Mask

-

• OVRE: Overrun Error Interrupt Mask

-

• FRAME: Framing Error Interrupt Mask

-

• PARE: Parity Error Interrupt Mask

-

• TIMEOUT: Time-out Interrupt Mask

-

• TXEMPTY: TXEMPTY Interrupt Mask

-

• ITER: Iteration Interrupt Enable

-

• TXBUFE: Buffer Empty Interrupt Mask

-

• RXBUFF: Buffer Full Interrupt Mask

-

• NACK: Non Acknowledge Interrupt Mask

-

• RIIC: Ring Indicator Input Change Mask

-

• DSRIC: Data Set Ready Input Change Mask

-

• DCDIC: Data Carrier Detect Input Change Interrupt Mask

-

• CTSIC: Clear to Send Input Change Interrupt Mask

-

• MANE: Manchester Error Interrupt Mask

-

• _

-

USART1 Channel Status Register

Name: USART1_CSR

Access: read-only

Address: 0xFFFC4014

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	MANERR
23	22	21	20	19	18	17	16
CTS	DCD	DSR	RI	CTSIC	DCDIC	DSRIC	RIIC
15	14	13	12	11	10	9	8
-	-	NACK	RXBUFF	TXBUFE	ITER	TXEMPTY	TIMEOUT
7	6	5	4	3	2	1	0
PARE	FRAME	OVRE	ENDTX	ENDRX	RXBRK	TXRDY	RXRDY

• RXRDY: Receiver Ready
• 0 = No complete character has been received since the last read of US_RHR or the receiver is disabled. If characters were being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled.
• 1 = At least one complete character has been received and US_RHR has not yet been read.
• TXRDY: Transmitter Ready
• 0 = A character is in the US_THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1.
• 1 = There is no character in the US_THR.
• RXBRK: Break Received/End of Break
• 0 = No Break received or End of Break detected since the last RSTSTA.
• 1 = Break Received or End of Break detected since the last RSTSTA.
• ENDRX: End of Receiver Transfer
• 0 = The End of Transfer signal from the Receive PDC channel is inactive.
• 1 = The End of Transfer signal from the Receive PDC channel is active.
• ENDTX: End of Transmitter Transfer
• 0 = The End of Transfer signal from the Transmit PDC channel is inactive.
• 1 = The End of Transfer signal from the Transmit PDC channel is active.
• OVRE: Overrun Error
• 0 = No overrun error has occurred since the last RSTSTA.
• 1 = At least one overrun error has occurred since the last RSTSTA.
• FRAME: Framing Error
• 0 = No stop bit has been detected low since the last RSTSTA.
• 1 = At least one stop bit has been detected low since the last RSTSTA.
• PARE: Parity Error
• 0 = No parity error has been detected since the last RSTSTA.
• 1 = At least one parity error has been detected since the last RSTSTA.
• TIMEOUT: Receiver Time-out
• 0 = There has not been a time-out since the last Start Time-out command (STTTO in US_CR) or the Time-out Register is 0.
• 1 = There has been a time-out since the last Start Time-out command (STTTO in US_CR).
• TXEMPTY: Transmitter Empty
• 0 = There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled.
• 1 = There are no characters in US_THR, nor in the Transmit Shift Register.
• ITER: Max number of Repetitions Reached
• 0 = Maximum number of repetitions has not been reached since the last RSTSTA.
• 1 = Maximum number of repetitions has been reached since the last RSTSTA.
• TXBUFE: Transmission Buffer Empty
• 0 = The signal Buffer Empty from the Transmit PDC channel is inactive.
• 1 = The signal Buffer Empty from the Transmit PDC channel is active.
• RXBUFF: Reception Buffer Full
• 0 = The signal Buffer Full from the Receive PDC channel is inactive.
• 1 = The signal Buffer Full from the Receive PDC channel is active.
• NACK: Non Acknowledge
• 0 = No Non Acknowledge has not been detected since the last RSTNACK.
• 1 = At least one Non Acknowledge has been detected since the last RSTNACK.
• RIIC: Ring Indicator Input Change Flag
• 0 = No input change has been detected on the RI pin since the last read of US_CSR.
• 1 = At least one input change has been detected on the RI pin since the last read of US_CSR.
• DSRIC: Data Set Ready Input Change Flag
• 0 = No input change has been detected on the DSR pin since the last read of US_CSR.
• 1 = At least one input change has been detected on the DSR pin since the last read of US_CSR.
• DCDIC: Data Carrier Detect Input Change Flag
• 0 = No input change has been detected on the DCD pin since the last read of US_CSR.
• 1 = At least one input change has been detected on the DCD pin since the last read of US_CSR.
• CTSIC: Clear to Send Input Change Flag
• 0 = No input change has been detected on the CTS pin since the last read of US_CSR.
• 1 = At least one input change has been detected on the CTS pin since the last read of US_CSR.
• RI: Image of RI Input
• 0 = RI is at 0.
• 1 = RI is at 1.
• DSR: Image of DSR Input
• 0 = DSR is at 0
• 1 = DSR is at 1.
• DCD: Image of DCD Input
• 0 = DCD is at 0.
• 1 = DCD is at 1.
• CTS: Image of CTS Input
• 0 = CTS is at 0.
• 1 = CTS is at 1.
• MANERR: Manchester Error
• 0 = No Manchester error has been detected since the last RSTSTA.
• 1 = At least one Manchester error has been detected since the last RSTSTA.

USART1 Receiver Holding Register

Name: USART1_RHR

Access: read-only

Address: 0xFFFC4018

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
RXSYNH	-	-	-	-	-	-	RXCHR
7	6	5	4	3	2	1	0
RXCHR

• RXCHR: Received Character

-

• RXSYNH: Received Sync
• 0 = Last Character received is a Data.
• 1 = Last Character received is a Command.

USART1 Transmitter Holding Register

Name: USART1_THR

Access: write-only

Address: 0xFFFC401C

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
TXSYNH	-	-	-	-	-	-	TXCHR
7	6	5	4	3	2	1	0
TXCHR

• TXCHR: Character to be Transmitted

-

• TXSYNH: Sync Field to be transmitted
• 0 = The next character sent is encoded as a data. Start Frame Delimiter is DATA SYNC.
• 1 = The next character sent is encoded as a command. Start Frame Delimiter is COMMAND SYNC.

USART1 Baud Rate Generator Register

Name: USART1_BRGR

Access: read-write

Address: 0xFFFC4020

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	FP_
15	14	13	12	11	10	9	8
CD
7	6	5	4	3	2	1	0
CD

• CD: Clock Divider

-

• FP_

-

USART1 Receiver Time-out Register

Name: USART1_RTOR

Access: read-write

Address: 0xFFFC4024

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
TO
7	6	5	4	3	2	1	0
TO

• TO: Time-out Value

-

USART1 Transmitter Timeguard Register

Name: USART1_TTGR

Access: read-write

Address: 0xFFFC4028

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
TG

• TG: Timeguard Value

-

USART1 FI DI Ratio Register

Name: USART1_FIDI

Access: read-write

Address: 0xFFFC4040

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	FI_DI_RATIO
7	6	5	4	3	2	1	0
FI_DI_RATIO

• FI_DI_RATIO: FI Over DI Ratio Value

-

USART1 Number of Errors Register

Name: USART1_NER

Access: read-only

Address: 0xFFFC4044

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
NB_ERRORS

• NB_ERRORS: Number of Errors

-

USART1 IrDA Filter Register

Name: USART1_IF

Access: read-write

Address: 0xFFFC404C

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
IRDA_FILTER

• IRDA_FILTER: IrDA Filter

-

USART1 Manchester Encoder Decoder Register

Name: USART1_MAN

Access: read-write

Address: 0xFFFC4050

31	30	29	28	27	26	25	24
-	DRIFT	STUCKTO1	RX_MPOL	-	-	RX_PP
23	22	21	20	19	18	17	16
-	-	-	-	RX_PL
15	14	13	12	11	10	9	8
-	-	-	TX_MPOL	-	-	TX_PP
7	6	5	4	3	2	1	0
-	-	-	-	TX_PL

• TX_PL: Transmitter Preamble Length

-

• TX_PP: Transmitter Preamble Pattern
• 0x0 = ALL_ONE
• 0x1 = ALL_ZERO
• 0x2 = ZERO_ONE
• 0x3 = ONE_ZERO
• TX_MPOL: Transmitter Manchester Polarity
• 0 = Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition.
• 1 = Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition.
• RX_PL: Receiver Preamble Length

-

• RX_PP: Receiver Preamble Pattern detected
• 0x0 = ALL_ONE
• 0x1 = ALL_ZERO
• 0x2 = ZERO_ONE
• 0x3 = ONE_ZERO
• RX_MPOL: Receiver Manchester Polarity
• 0 = Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition.
• 1 = Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition.
• STUCKTO1

-

• DRIFT: Drift compensation
• 0 = The USART can not recover from an important clock drift
• 1 = The USART can recover from clock drift. The 16X clock mode must be enabled.

USART1 Version Register

Name: USART1_VERSION

Access: read-only

Address: 0xFFFC40FC

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	MFN
15	14	13	12	11	10	9	8
-	-	-	-	VERSION
7	6	5	4	3	2	1	0
VERSION

• VERSION

-

• MFN

-

USART1 Receive Pointer Register

Name: USART1_RPR

Access: read-write

Address: 0xFFFC4100

31	30	29	28	27	26	25	24
RXPTR
23	22	21	20	19	18	17	16
RXPTR
15	14	13	12	11	10	9	8
RXPTR
7	6	5	4	3	2	1	0
RXPTR

• RXPTR: Receive Pointer Address

-

USART1 Receive Counter Register

Name: USART1_RCR

Access: read-write

Address: 0xFFFC4104

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
RXCTR
7	6	5	4	3	2	1	0
RXCTR

• RXCTR: Receive Counter Value

-

USART1 Transmit Pointer Register

Name: USART1_TPR

Access: read-write

Address: 0xFFFC4108

31	30	29	28	27	26	25	24
TXPTR
23	22	21	20	19	18	17	16
TXPTR
15	14	13	12	11	10	9	8
TXPTR
7	6	5	4	3	2	1	0
TXPTR

• TXPTR: Transmit Pointer Address

-

USART1 Transmit Counter Register

Name: USART1_TCR

Access: read-write

Address: 0xFFFC410C

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
TXCTR
7	6	5	4	3	2	1	0
TXCTR

• TXCTR: Transmit Counter Value

-

USART1 Receive Next Pointer Register

Name: USART1_RNPR

Access: read-write

Address: 0xFFFC4110

31	30	29	28	27	26	25	24
RXNPTR
23	22	21	20	19	18	17	16
RXNPTR
15	14	13	12	11	10	9	8
RXNPTR
7	6	5	4	3	2	1	0
RXNPTR

• RXNPTR: Receive Next Pointer Address

-

USART1 Receive Next Counter Register

Name: USART1_RNCR

Access: read-write

Address: 0xFFFC4114

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
RXNCR
7	6	5	4	3	2	1	0
RXNCR

• RXNCR: Receive Next Counter Value

-

USART1 Transmit Next Pointer Register

Name: USART1_TNPR

Access: read-write

Address: 0xFFFC4118

31	30	29	28	27	26	25	24
TXNPTR
23	22	21	20	19	18	17	16
TXNPTR
15	14	13	12	11	10	9	8
TXNPTR
7	6	5	4	3	2	1	0
TXNPTR

• TXNPTR: Transmit Next Pointer Address

-

USART1 Transmit Next Counter Register

Name: USART1_TNCR

Access: read-write

Address: 0xFFFC411C

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
TXNCR
7	6	5	4	3	2	1	0
TXNCR

• TXNCR: Transmit Next Counter Value

-

USART1 PDC Transfer Control Register

Name: USART1_PTCR

Access: write-only

Address: 0xFFFC4120

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	TXTDIS	TXTEN
7	6	5	4	3	2	1	0
-	-	-	-	-	-	RXTDIS	RXTEN

• RXTEN: Receiver Transfer Enable
• 0 = No effect.
• 1 = Enables the receiver PDC transfer requests if RXTDIS is not set.
• RXTDIS: Receiver Transfer Disable
• 0 = No effect.
• 1 = Disables the receiver PDC transfer requests.
• TXTEN: Transmitter Transfer Enable
• 0 = No effect.
• 1 = Enables the transmitter PDC transfer requests.
• TXTDIS: Transmitter Transfer Disable
• 0 = No effect.
• 1 = Disables the transmitter PDC transfer requests.

USART1 PDC Transfer Status Register

Name: USART1_PTSR

Access: read-only

Address: 0xFFFC4124

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	TXTEN
7	6	5	4	3	2	1	0
-	-	-	-	-	-	-	RXTEN

• RXTEN: Receiver Transfer Enable
• 0 = Receiver PDC transfer requests are disabled.
• 1 = Receiver PDC transfer requests are enabled.
• TXTEN: Transmitter Transfer Enable
• 0 = Transmitter PDC transfer requests are disabled.
• 1 = Transmitter PDC transfer requests are enabled.