Burst Flash Controller Interface Peripheral

BFC (AT91S_BFC) 0xFFFFFFC0 (AT91C_BASE_BFC)

BFC Software API (AT91S_BFC)

OffsetFieldDescription
0x0BFC_MRBFC Mode Register

BFC Register Description

BFC: AT91_REG BFC_MR BFC Mode Register

OffsetNameDescription
1..0BFC_BFCOM
AT91C_BFC_BFCOM		Burst Flash Controller Operating Mode
ValueLabelDescription
0BFC_BFCOM_DISABLED
AT91C_BFC_BFCOM_DISABLED
NPCS0 is driven by the SMC or remains high.
1BFC_BFCOM_ASYNC
AT91C_BFC_BFCOM_ASYNC
Asynchronous
2BFC_BFCOM_BURST_READ
AT91C_BFC_BFCOM_BURST_READ
Burst Read
3..2BFC_BFCC
AT91C_BFC_BFCC		Burst Flash Controller Operating Mode
ValueLabelDescription
1BFC_BFCC_MCK
AT91C_BFC_BFCC_MCK
Master Clock.
2BFC_BFCC_MCK_DIV_2
AT91C_BFC_BFCC_MCK_DIV_2
Master Clock divided by 2.
3BFC_BFCC_MCK_DIV_4
AT91C_BFC_BFCC_MCK_DIV_4
Master Clock divided by 4.
7..4BFC_AVL
AT91C_BFC_AVL		Address Valid Latency
This field defines the number of BFC Clock Cycles required to wait until the first data is received.
This number equals (AVL+1).
10..8BFC_PAGES
AT91C_BFC_PAGES		Page Size
This field defines the page size handling and the page size.
ValueLabelDescription
0BFC_PAGES_NO_PAGE
AT91C_BFC_PAGES_NO_PAGE
No page handling.
1BFC_PAGES_16
AT91C_BFC_PAGES_16
16 bytes page size.
2BFC_PAGES_32
AT91C_BFC_PAGES_32
32 bytes page size.
3BFC_PAGES_64
AT91C_BFC_PAGES_64
64 bytes page size.
4BFC_PAGES_128
AT91C_BFC_PAGES_128
128 bytes page size.
5BFC_PAGES_256
AT91C_BFC_PAGES_256
256 bytes page size.
6BFC_PAGES_512
AT91C_BFC_PAGES_512
512 bytes page size.
7BFC_PAGES_1024
AT91C_BFC_PAGES_1024
1024 bytes page size.
13..12BFC_OEL
AT91C_BFC_OEL		Output Enable Latency
This field defines the number of idle cycles inserted after each level change on the bfoe output enable signal.
OEL is between 1 and 3.
16BFC_BAAEN
AT91C_BFC_BAAEN		Burst Address Advance Enable
0 = The burst clock is enabled to increment the burst address or, disabled to remain at the same address.
1 = The burst clock is continuous and the burst address advance is controlled with the bfbaa pin.
17BFC_BFOEH
AT91C_BFC_BFOEH		Burst Flash Output Enable Handling
18BFC_MUXEN
AT91C_BFC_MUXEN		Multiplexed Bus Enable
0 = The address and data buses operate independently.
1 = The address and data buses are multiplexed.
Actually, the address is presented on both the data bus and the address bus when the bfavd signal is asserted.
19BFC_RDYEN
AT91C_BFC_RDYEN		Ready Enable Mode
0 = The bfrdy input signal at the BFC input is ignored.
1 = The bfrdy input signal is used as an indicator of data availability in the next cycle.