Static Memory Controller 2 Interface Peripheral

SMC2 (AT91S_SMC2) 0xFFFFFF70 (AT91C_BASE_SMC2)
SignalSymbolPIO controllerDescription
NCS4_CFCS(AT91C_PC10_NCS4_CFCS)PIOC Periph: A Bit: 10Compact Flash Chip Select
A25_CFRNW(AT91C_PC9_A25_CFRNW)PIOC Periph: A Bit: 9Address Bus[25] / Compact Flash Read Not Write
NCS6_CFCE2(AT91C_PC12_NCS6_CFCE2)PIOC Periph: A Bit: 12Chip Select 6 / Compact Flash Chip Enable 2
NCS5_CFCE1(AT91C_PC11_NCS5_CFCE1)PIOC Periph: A Bit: 11Chip Select 5 / Compact Flash Chip Enable 1

FunctionDescription
AT91F_SMC2_CfgPIOConfigure PIO controllers to drive SMC2 signals


SMC2 Software API (AT91S_SMC2)

OffsetFieldDescription
0x0SMC2_CSR[8] (SMC2_CSR)SMC2 Chip Select Register

SMC2 Register Description

SMC2: AT91_REG SMC2_CSR SMC2 Chip Select Register

OffsetNameDescription
6..0SMC2_NWS
AT91C_SMC2_NWS		Number of Wait States
This field defines the Read and Write signal pulse length from 1 cycle up to 128 cycles.
7SMC2_WSEN
AT91C_SMC2_WSEN		Wait State Enable
0 = Wait States are disabled.
1 = Wait States are enabled.
11..8SMC2_TDF
AT91C_SMC2_TDF		Data Float Time
The external bus is marked occupied and cannot be used by another chip select during TDF cycle.
Up to 15 cycles can be defined.
12SMC2_BAT
AT91C_SMC2_BAT		Byte Access Type
This field is used only if DBW defines a 16- or 32-bit data bus.
0 = Chip Select line is connected to two 8-bit wide devices or four 8-bit devices.
1 = Chip Select line is connected to a 16-bit wide device.
13SMC2_DBW
AT91C_SMC2_DBW		Data Bus Width
ValueLabelDescription
1SMC2_DBW_16
AT91C_SMC2_DBW_16
16-bit.
2SMC2_DBW_8
AT91C_SMC2_DBW_8
8-bit.
15SMC2_DRP
AT91C_SMC2_DRP		Data Read Protocol
0 = Standard Read Protocol is used.
1 = Early Read Protocol is used.
17..16SMC2_ACSS
AT91C_SMC2_ACSS		Address to Chip Select Setup
ValueLabelDescription
0SMC2_ACSS_STANDARD
AT91C_SMC2_ACSS_STANDARD
Standard, asserted at the beginning of the access and deasserted at the end.
1SMC2_ACSS_1_CYCLE
AT91C_SMC2_ACSS_1_CYCLE
One cycle less at the beginning and the end of the access.
2SMC2_ACSS_2_CYCLES
AT91C_SMC2_ACSS_2_CYCLES
Two cycles less at the beginning and the end of the access.
3SMC2_ACSS_3_CYCLES
AT91C_SMC2_ACSS_3_CYCLES
Three cycles less at the beginning and the end of the access.
26..24SMC2_RWSETUP
AT91C_SMC2_RWSETUP		Read and Write Signal Setup Time
31..29SMC2_RWHOLD
AT91C_SMC2_RWHOLD		Read and Write Signal Hold Time