| Periph ID AIC | Symbol | Description |
|---|---|---|
| 1 | (AT91C_ID_SYS) | System Peripheral |
| Function | Description |
|---|---|
| AT91F_ST_CfgPMC | Enable Peripheral clock in PMC for ST |
| Offset | Field | Description |
|---|---|---|
| 0x0 | ST_CR | Control Register |
| 0x4 | ST_PIMR | Period Interval Mode Register |
| 0x8 | ST_WDMR | Watchdog Mode Register |
| 0xC | ST_RTMR | Real-time Mode Register |
| 0x10 | ST_SR | Status Register |
| 0x14 | ST_IER | Interrupt Enable Register |
| 0x18 | ST_IDR | Interrupt Disable Register |
| 0x1C | ST_IMR | Interrupt Mask Register |
| 0x20 | ST_RTAR | Real-time Alarm Register |
| 0x24 | ST_CRTR | Current Real-time Register |
| Function | Description |
|---|---|
| AT91F_ST_DisableIt | Disable system timer interrupt |
| AT91F_ST_GetInterruptMaskStatus | Return ST Interrupt Mask Status |
| AT91F_ST_IsInterruptMasked | Test if ST Interrupt is Masked |
| AT91F_ST_EnableIt | Enable system timer interrupt |
| AT91F_ST_SetPeriodInterval | Set Periodic Interval Interrupt (period in ms) |
| Offset | Name | Description |
|---|---|---|
| 0 | ST_WDRST AT91C_ST_WDRST | Watchdog Timer Restart 0 = No effect. 1 = Reload the start-up value in the Watchdog Timer. |
| Offset | Name | Description |
|---|---|---|
| 15..0 | ST_PIV AT91C_ST_PIV | Watchdog Timer Restart Defines the value loaded in the 16-bit counter of the Period Interval Timer. The maximum period is obtained by pro-gramming PIV at 0x0 corresponding to 65536 Slow Clock cycles. |
| Offset | Name | Description |
|---|---|---|
| 15..0 | ST_WDV AT91C_ST_WDV | Watchdog Timer Restart Defines the value loaded in the 16-bit counter. The maximum period is obtained by programming WDV to 0x0 corre-sponding to 65536 * 128 Slow Clock cycles. |
| 16 | ST_RSTEN AT91C_ST_RSTEN | Reset Enable 0 = No reset is generated when a watchdog overflow occurs. 1 = An internal reset is generated when a watchdog overflow occurs. |
| 17 | ST_EXTEN AT91C_ST_EXTEN | External Signal Assertion Enable 0 = The NWDOVF is not tied low when a watchdog overflow occurs. 1 = The NWDOVF is tied low during 8 Slow Clock cycles when a watchdog overflow occurs. |
| Offset | Name | Description |
|---|---|---|
| 15..0 | ST_RTPRES AT91C_ST_RTPRES | Real-time Timer Prescaler Value Defines the number of SLCK periods required to increment the Real-time Timer. The maximum period is obtained by programming RTPRES to 0x0 corresponding to 65536 Slow Clock cycles. |
| Offset | Name | Description |
|---|---|---|
| 0 | ST_PITS AT91C_ST_PITS | Period Interval Timer Interrupt 0 = The Period Interval Timer has not reached 0 since the last read of the Status Register. 1 = The Period Interval Timer has reached 0 since the last read of the Status Register. |
| 1 | ST_WDOVF AT91C_ST_WDOVF | Watchdog Overflow 0 = The Watchdog Timer has not reached 0 since the last read of the Status Register. 1 = The Watchdog Timer has reached 0 since the last read of the Status Register. |
| 2 | ST_RTTINC AT91C_ST_RTTINC | Real-time Timer Increment 0 = The Real-time Timer has not been incremented since the last read of the Status Register. 1 = The Real-time Timer has been incremented since the last read of the Status Register. |
| 3 | ST_ALMS AT91C_ST_ALMS | Alarm Status 0 = No alarm compare has been detected since the last read of the Status Register. 1 = Alarm compare has been detected since the last read of the Status Register. |
| Offset | Name | Description |
|---|---|---|
| 0 | ST_PITS AT91C_ST_PITS | Period Interval Timer Interrupt 0 = The Period Interval Timer has not reached 0 since the last read of the Status Register. 1 = The Period Interval Timer has reached 0 since the last read of the Status Register. |
| 1 | ST_WDOVF AT91C_ST_WDOVF | Watchdog Overflow 0 = The Watchdog Timer has not reached 0 since the last read of the Status Register. 1 = The Watchdog Timer has reached 0 since the last read of the Status Register. |
| 2 | ST_RTTINC AT91C_ST_RTTINC | Real-time Timer Increment 0 = The Real-time Timer has not been incremented since the last read of the Status Register. 1 = The Real-time Timer has been incremented since the last read of the Status Register. |
| 3 | ST_ALMS AT91C_ST_ALMS | Alarm Status 0 = No alarm compare has been detected since the last read of the Status Register. 1 = Alarm compare has been detected since the last read of the Status Register. |
| Offset | Name | Description |
|---|---|---|
| 0 | ST_PITS AT91C_ST_PITS | Period Interval Timer Interrupt 0 = The Period Interval Timer has not reached 0 since the last read of the Status Register. 1 = The Period Interval Timer has reached 0 since the last read of the Status Register. |
| 1 | ST_WDOVF AT91C_ST_WDOVF | Watchdog Overflow 0 = The Watchdog Timer has not reached 0 since the last read of the Status Register. 1 = The Watchdog Timer has reached 0 since the last read of the Status Register. |
| 2 | ST_RTTINC AT91C_ST_RTTINC | Real-time Timer Increment 0 = The Real-time Timer has not been incremented since the last read of the Status Register. 1 = The Real-time Timer has been incremented since the last read of the Status Register. |
| 3 | ST_ALMS AT91C_ST_ALMS | Alarm Status 0 = No alarm compare has been detected since the last read of the Status Register. 1 = Alarm compare has been detected since the last read of the Status Register. |
| Offset | Name | Description |
|---|---|---|
| 0 | ST_PITS AT91C_ST_PITS | Period Interval Timer Interrupt 0 = The Period Interval Timer has not reached 0 since the last read of the Status Register. 1 = The Period Interval Timer has reached 0 since the last read of the Status Register. |
| 1 | ST_WDOVF AT91C_ST_WDOVF | Watchdog Overflow 0 = The Watchdog Timer has not reached 0 since the last read of the Status Register. 1 = The Watchdog Timer has reached 0 since the last read of the Status Register. |
| 2 | ST_RTTINC AT91C_ST_RTTINC | Real-time Timer Increment 0 = The Real-time Timer has not been incremented since the last read of the Status Register. 1 = The Real-time Timer has been incremented since the last read of the Status Register. |
| 3 | ST_ALMS AT91C_ST_ALMS | Alarm Status 0 = No alarm compare has been detected since the last read of the Status Register. 1 = Alarm compare has been detected since the last read of the Status Register. |
| Offset | Name | Description |
|---|---|---|
| 19..0 | ST_ALMV AT91C_ST_ALMV | Alarm Value Value Defines the Alarm value compared with the Real-time Timer. The maximum delay before ALMS status bit activation is obtained by programming ALMV to 0x0 corresponding to 1048576 seconds. |
| Offset | Name | Description |
|---|---|---|
| 19..0 | ST_CRTV AT91C_ST_CRTV | Current Real-time Value Returns the current value of the Real-time Timer. |