Timer Counter Channel Interface Peripheral

TC5 (AT91S_TC) 0xFFFA4080 (AT91C_BASE_TC5)

Periph ID AIC	Symbol	Description
22	(AT91C_ID_TC5)	Timer Counter 5

Function	Description
AT91F_TC5_CfgPMC	Enable Peripheral clock in PMC for TC5

TC4 (AT91S_TC) 0xFFFA4040 (AT91C_BASE_TC4)

Periph ID AIC	Symbol	Description
21	(AT91C_ID_TC4)	Timer Counter 4

Function	Description
AT91F_TC4_CfgPMC	Enable Peripheral clock in PMC for TC4

TC3 (AT91S_TC) 0xFFFA4000 (AT91C_BASE_TC3)

Periph ID AIC	Symbol	Description
20	(AT91C_ID_TC3)	Timer Counter 3

Function	Description
AT91F_TC3_CfgPMC	Enable Peripheral clock in PMC for TC3

TC2 (AT91S_TC) 0xFFFA0080 (AT91C_BASE_TC2)

Periph ID AIC	Symbol	Description
19	(AT91C_ID_TC2)	Timer Counter 2

Function	Description
AT91F_TC2_CfgPMC	Enable Peripheral clock in PMC for TC2

TC1 (AT91S_TC) 0xFFFA0040 (AT91C_BASE_TC1)

Periph ID AIC	Symbol	Description
18	(AT91C_ID_TC1)	Timer Counter 1

Function	Description
AT91F_TC1_CfgPMC	Enable Peripheral clock in PMC for TC1

TC0 (AT91S_TC) 0xFFFA0000 (AT91C_BASE_TC0)

Periph ID AIC	Symbol	Description
17	(AT91C_ID_TC0)	Timer Counter 0

Function	Description
AT91F_TC0_CfgPMC	Enable Peripheral clock in PMC for TC0

TC Software API (AT91S_TC)

Offset	Field	Description
0x0	TC_CCR	Channel Control Register
0x4	TC_CMR	Channel Mode Register
0x10	TC_CV	Counter Value
0x14	TC_RA	Register A
0x18	TC_RB	Register B
0x1C	TC_RC	Register C
0x20	TC_SR	Status Register
0x24	TC_IER	Interrupt Enable Register
0x28	TC_IDR	Interrupt Disable Register
0x2C	TC_IMR	Interrupt Mask Register

Function	Description
AT91F_TC_GetInterruptMaskStatus	Return TC Interrupt Mask Status
AT91F_TC_IsInterruptMasked	Test if TC Interrupt is Masked
AT91F_TC_InterruptDisable	Disable TC Interrupt
AT91F_TC_InterruptEnable	Enable TC Interrupt

TC Register Description

TC: AT91_REG TC_CCR Channel Control Register

TC5 AT91C_TC5_CCR 0xFFFA4080

TC4 AT91C_TC4_CCR 0xFFFA4040

TC3 AT91C_TC3_CCR 0xFFFA4000

TC2 AT91C_TC2_CCR 0xFFFA0080

TC1 AT91C_TC1_CCR 0xFFFA0040

TC0 AT91C_TC0_CCR 0xFFFA0000

Offset	Name	Description
0	TC_CLKEN AT91C_TC_CLKEN	Counter Clock Enable Command 0 = No effect. 1 = Enables the clock if CLKDIS is not 1.
1	TC_CLKDIS AT91C_TC_CLKDIS	Counter Clock Disable Command 0 = No effect. 1 = Disables the clock.
2	TC_SWTRG AT91C_TC_SWTRG	Software Trigger Command 0 = No effect. 1 = A software trigger is performed: the counter is reset and clock is started.

TC: AT91_REG TC_CMR Channel Mode Register

TC5 AT91C_TC5_CMR 0xFFFA4084

TC4 AT91C_TC4_CMR 0xFFFA4044

TC3 AT91C_TC3_CMR 0xFFFA4004

TC2 AT91C_TC2_CMR 0xFFFA0084

TC1 AT91C_TC1_CMR 0xFFFA0044

TC0 AT91C_TC0_CMR 0xFFFA0004

Offset

Name

Description

TC_CPCSTOP
AT91C_TC_CPCSTOP

Counter Clock Stopped with RC Compare
0 = Counter clock is not stopped when counter reaches RC.
1 = Counter clock is stopped when counter reaches RC.

TC_CPCDIS
AT91C_TC_CPCDIS

Counter Clock Disable with RC Compare
0 = Counter clock is not disabled when counter reaches RC.
1 = Counter clock is disabled when counter reaches RC.

9..8

TC_EEVTEDG
AT91C_TC_EEVTEDG

External Event Edge Selection

Value	Label	Description
0	TC_EEVTEDG_NONE AT91C_TC_EEVTEDG_NONE	Edge: None
1	TC_EEVTEDG_RISING AT91C_TC_EEVTEDG_RISING	Edge: rising edge
2	TC_EEVTEDG_FALLING AT91C_TC_EEVTEDG_FALLING	Edge: falling edge
3	TC_EEVTEDG_BOTH AT91C_TC_EEVTEDG_BOTH	Edge: each edge

11..10

TC_EEVT
AT91C_TC_EEVT

External Event Selection

Value	Label	Description
0	TC_EEVT_NONE AT91C_TC_EEVT_NONE	Signal selected as external event: TIOB TIOB direction: input
1	TC_EEVT_RISING AT91C_TC_EEVT_RISING	Signal selected as external event: XC0 TIOB direction: output
2	TC_EEVT_FALLING AT91C_TC_EEVT_FALLING	Signal selected as external event: XC1 TIOB direction: output
3	TC_EEVT_BOTH AT91C_TC_EEVT_BOTH	Signal selected as external event: XC2 TIOB direction: output

TC_ENETRG
AT91C_TC_ENETRG

External Event Trigger enable
0 = The external event has no effect on the counter and its clock. In this case, the selected external event only controls the TIOA output.
1 = The external event resets the counter and starts the counter clock.

14..13

TC_WAVESEL
AT91C_TC_WAVESEL

Waveform Selection

Value	Label	Description
0	TC_WAVESEL_UP AT91C_TC_WAVESEL_UP	UP mode without atomatic trigger on RC Compare
1	TC_WAVESEL_UP_AUTO AT91C_TC_WAVESEL_UP_AUTO	UP mode with automatic trigger on RC Compare
2	TC_WAVESEL_UPDOWN AT91C_TC_WAVESEL_UPDOWN	UPDOWN mode without automatic trigger on RC Compare
3	TC_WAVESEL_UPDOWN_AUTO AT91C_TC_WAVESEL_UPDOWN_AUTO	UPDOWN mode with automatic trigger on RC Compare

TC_CPCTRG
AT91C_TC_CPCTRG

RC Compare Trigger Enable
0 = RC Compare has no effect on the counter and its clock.
1 = RC Compare resets the counter and starts the counter clock.

TC_WAVE
AT91C_TC_WAVE

0 = Capture Mode is enabled.
1 = Capture Mode is disabled (Waveform Mode is enabled).
0 = Waveform Mode is disabled (Capture Mode is enabled).
1 = Waveform Mode is enabled.

17..16

TC_ACPA
AT91C_TC_ACPA

RA Compare Effect on TIOA

Value	Label	Description
0	TC_ACPA_NONE AT91C_TC_ACPA_NONE	Effect: none
1	TC_ACPA_SET AT91C_TC_ACPA_SET	Effect: set
2	TC_ACPA_CLEAR AT91C_TC_ACPA_CLEAR	Effect: clear
3	TC_ACPA_TOGGLE AT91C_TC_ACPA_TOGGLE	Effect: toggle

19..18

TC_ACPC
AT91C_TC_ACPC

RC Compare Effect on TIOA

Value	Label	Description
0	TC_ACPC_NONE AT91C_TC_ACPC_NONE	Effect: none
1	TC_ACPC_SET AT91C_TC_ACPC_SET	Effect: set
2	TC_ACPC_CLEAR AT91C_TC_ACPC_CLEAR	Effect: clear
3	TC_ACPC_TOGGLE AT91C_TC_ACPC_TOGGLE	Effect: toggle

21..20

TC_AEEVT
AT91C_TC_AEEVT

External Event Effect on TIOA

Value	Label	Description
0	TC_AEEVT_NONE AT91C_TC_AEEVT_NONE	Effect: none
1	TC_AEEVT_SET AT91C_TC_AEEVT_SET	Effect: set
2	TC_AEEVT_CLEAR AT91C_TC_AEEVT_CLEAR	Effect: clear
3	TC_AEEVT_TOGGLE AT91C_TC_AEEVT_TOGGLE	Effect: toggle

23..22

TC_ASWTRG
AT91C_TC_ASWTRG

Software Trigger Effect on TIOA

Value	Label	Description
0	TC_ASWTRG_NONE AT91C_TC_ASWTRG_NONE	Effect: none
1	TC_ASWTRG_SET AT91C_TC_ASWTRG_SET	Effect: set
2	TC_ASWTRG_CLEAR AT91C_TC_ASWTRG_CLEAR	Effect: clear
3	TC_ASWTRG_TOGGLE AT91C_TC_ASWTRG_TOGGLE	Effect: toggle

25..24

TC_BCPB
AT91C_TC_BCPB

RB Compare Effect on TIOB

Value	Label	Description
0	TC_BCPB_NONE AT91C_TC_BCPB_NONE	Effect: none
1	TC_BCPB_SET AT91C_TC_BCPB_SET	Effect: set
2	TC_BCPB_CLEAR AT91C_TC_BCPB_CLEAR	Effect: clear
3	TC_BCPB_TOGGLE AT91C_TC_BCPB_TOGGLE	Effect: toggle

27..26

TC_BCPC
AT91C_TC_BCPC

RC Compare Effect on TIOB

Value	Label	Description
0	TC_BCPC_NONE AT91C_TC_BCPC_NONE	Effect: none
1	TC_BCPC_SET AT91C_TC_BCPC_SET	Effect: set
2	TC_BCPC_CLEAR AT91C_TC_BCPC_CLEAR	Effect: clear
3	TC_BCPC_TOGGLE AT91C_TC_BCPC_TOGGLE	Effect: toggle

29..28

TC_BEEVT
AT91C_TC_BEEVT

External Event Effect on TIOB

Value	Label	Description
0	TC_BEEVT_NONE AT91C_TC_BEEVT_NONE	Effect: none
1	TC_BEEVT_SET AT91C_TC_BEEVT_SET	Effect: set
2	TC_BEEVT_CLEAR AT91C_TC_BEEVT_CLEAR	Effect: clear
3	TC_BEEVT_TOGGLE AT91C_TC_BEEVT_TOGGLE	Effect: toggle

31..30

TC_BSWTRG
AT91C_TC_BSWTRG

Software Trigger Effect on TIOB

Value	Label	Description
0	TC_BSWTRG_NONE AT91C_TC_BSWTRG_NONE	Effect: none
1	TC_BSWTRG_SET AT91C_TC_BSWTRG_SET	Effect: set
2	TC_BSWTRG_CLEAR AT91C_TC_BSWTRG_CLEAR	Effect: clear
3	TC_BSWTRG_TOGGLE AT91C_TC_BSWTRG_TOGGLE	Effect: toggle

TC: AT91_REG TC_CV Counter Value

TC5 AT91C_TC5_CV 0xFFFA4090

TC4 AT91C_TC4_CV 0xFFFA4050

TC3 AT91C_TC3_CV 0xFFFA4010

TC2 AT91C_TC2_CV 0xFFFA0090

TC1 AT91C_TC1_CV 0xFFFA0050

TC0 AT91C_TC0_CV 0xFFFA0010

0-65535 Counter Value contains the counter value in real time.

TC: AT91_REG TC_RA Register A

TC5 AT91C_TC5_RA 0xFFFA4094

TC4 AT91C_TC4_RA 0xFFFA4054

TC3 AT91C_TC3_RA 0xFFFA4014

TC2 AT91C_TC2_RA 0xFFFA0094

TC1 AT91C_TC1_RA 0xFFFA0054

TC0 AT91C_TC0_RA 0xFFFA0014

TC Register A contains the Register A value in real time

TC: AT91_REG TC_RB Register B

TC5 AT91C_TC5_RB 0xFFFA4098

TC4 AT91C_TC4_RB 0xFFFA4058

TC3 AT91C_TC3_RB 0xFFFA4018

TC2 AT91C_TC2_RB 0xFFFA0098

TC1 AT91C_TC1_RB 0xFFFA0058

TC0 AT91C_TC0_RB 0xFFFA0018

TC Register B contains the Register B value in real time

TC: AT91_REG TC_RC Register C

TC5 AT91C_TC5_RC 0xFFFA409C

TC4 AT91C_TC4_RC 0xFFFA405C

TC3 AT91C_TC3_RC 0xFFFA401C

TC2 AT91C_TC2_RC 0xFFFA009C

TC1 AT91C_TC1_RC 0xFFFA005C

TC0 AT91C_TC0_RC 0xFFFA001C

TC Register C contains the Register C value in real time

TC: AT91_REG TC_SR Status Register

TC5 AT91C_TC5_SR 0xFFFA40A0

TC4 AT91C_TC4_SR 0xFFFA4060

TC3 AT91C_TC3_SR 0xFFFA4020

TC2 AT91C_TC2_SR 0xFFFA00A0

TC1 AT91C_TC1_SR 0xFFFA0060

TC0 AT91C_TC0_SR 0xFFFA0020

Offset	Name	Description
0	TC_COVFS AT91C_TC_COVFS	Counter Overflow 0 = No counter overflow has occurred since the last read of the Status Register. 1 = A counter overflow has occurred since the last read of the Status Register.
1	TC_LOVRS AT91C_TC_LOVRS	Load Overrun 0 = Load overrun has not occurred since the last read of the Status Register or WAVE = 1. 1 = RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the Sta-tus Register, if WAVE = 0.
2	TC_CPAS AT91C_TC_CPAS	RA Compare 0 = RA Compare has not occurred since the last read of the Status Register or WAVE = 0. 1 = RA Compare has occurred since the last read of the Status Register, if WAVE = 1.
3	TC_CPBS AT91C_TC_CPBS	RB Compare 0 = RB Compare has not occurred since the last read of the Status Register or WAVE = 0. 1 = RB Compare has occurred since the last read of the Status Register, if WAVE = 1.
4	TC_CPCS AT91C_TC_CPCS	RC Compare 0 = RC Compare has not occurred since the last read of the Status Register. 1 = RC Compare has occurred since the last read of the Status Register.
5	TC_LDRAS AT91C_TC_LDRAS	RA Loading 0 = RA Load has not occurred since the last read of the Status Register or WAVE = 1. 1 = RA Load has occurred since the last read of the Status Register, if WAVE = 0.
6	TC_LDRBS AT91C_TC_LDRBS	RB Loading 0 = RB Load has not occurred since the last read of the Status Register or WAVE = 1. 1 = RB Load has occurred since the last read of the Status Register, if WAVE = 0.
7	TC_ETRCS AT91C_TC_ETRCS	External Trigger 0 = External trigger has not occurred since the last read of the Status Register. 1 = External trigger has occurred since the last read of the Status Register.
16	TC_ETRGS AT91C_TC_ETRGS	Clock Enabling 0 = Clock is disabled. 1 = Clock is enabled.
17	TC_MTIOA AT91C_TC_MTIOA	TIOA Mirror 0 = TIOA is low. If WAVE = 0, this means that TIOA pin is low. If WAVE = 1, this means that TIOA is driven low. 1 = TIOA is high. If WAVE = 0, this means that TIOA pin is high. If WAVE = 1, this means that TIOA is driven high.
18	TC_MTIOB AT91C_TC_MTIOB	TIOA Mirror 0 = TIOB is low. If WAVE = 0, this means that TIOB pin is low. If WAVE = 1, this means that TIOB is driven low. 1 = TIOB is high. If WAVE = 0, this means that TIOB pin is high. If WAVE = 1, this means that TIOB is driven high.

TC: AT91_REG TC_IER Interrupt Enable Register

TC5 AT91C_TC5_IER 0xFFFA40A4

TC4 AT91C_TC4_IER 0xFFFA4064

TC3 AT91C_TC3_IER 0xFFFA4024

TC2 AT91C_TC2_IER 0xFFFA00A4

TC1 AT91C_TC1_IER 0xFFFA0064

TC0 AT91C_TC0_IER 0xFFFA0024

Offset	Name	Description
0	TC_COVFS AT91C_TC_COVFS	Counter Overflow 0 = No counter overflow has occurred since the last read of the Status Register. 1 = A counter overflow has occurred since the last read of the Status Register.
1	TC_LOVRS AT91C_TC_LOVRS	Load Overrun 0 = Load overrun has not occurred since the last read of the Status Register or WAVE = 1. 1 = RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the Sta-tus Register, if WAVE = 0.
2	TC_CPAS AT91C_TC_CPAS	RA Compare 0 = RA Compare has not occurred since the last read of the Status Register or WAVE = 0. 1 = RA Compare has occurred since the last read of the Status Register, if WAVE = 1.
3	TC_CPBS AT91C_TC_CPBS	RB Compare 0 = RB Compare has not occurred since the last read of the Status Register or WAVE = 0. 1 = RB Compare has occurred since the last read of the Status Register, if WAVE = 1.
4	TC_CPCS AT91C_TC_CPCS	RC Compare 0 = RC Compare has not occurred since the last read of the Status Register. 1 = RC Compare has occurred since the last read of the Status Register.
5	TC_LDRAS AT91C_TC_LDRAS	RA Loading 0 = RA Load has not occurred since the last read of the Status Register or WAVE = 1. 1 = RA Load has occurred since the last read of the Status Register, if WAVE = 0.
6	TC_LDRBS AT91C_TC_LDRBS	RB Loading 0 = RB Load has not occurred since the last read of the Status Register or WAVE = 1. 1 = RB Load has occurred since the last read of the Status Register, if WAVE = 0.
7	TC_ETRCS AT91C_TC_ETRCS	External Trigger 0 = External trigger has not occurred since the last read of the Status Register. 1 = External trigger has occurred since the last read of the Status Register.

TC: AT91_REG TC_IDR Interrupt Disable Register

TC5 AT91C_TC5_IDR 0xFFFA40A8

TC4 AT91C_TC4_IDR 0xFFFA4068

TC3 AT91C_TC3_IDR 0xFFFA4028

TC2 AT91C_TC2_IDR 0xFFFA00A8

TC1 AT91C_TC1_IDR 0xFFFA0068

TC0 AT91C_TC0_IDR 0xFFFA0028

Offset	Name	Description
0	TC_COVFS AT91C_TC_COVFS	Counter Overflow 0 = No counter overflow has occurred since the last read of the Status Register. 1 = A counter overflow has occurred since the last read of the Status Register.
1	TC_LOVRS AT91C_TC_LOVRS	Load Overrun 0 = Load overrun has not occurred since the last read of the Status Register or WAVE = 1. 1 = RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the Sta-tus Register, if WAVE = 0.
2	TC_CPAS AT91C_TC_CPAS	RA Compare 0 = RA Compare has not occurred since the last read of the Status Register or WAVE = 0. 1 = RA Compare has occurred since the last read of the Status Register, if WAVE = 1.
3	TC_CPBS AT91C_TC_CPBS	RB Compare 0 = RB Compare has not occurred since the last read of the Status Register or WAVE = 0. 1 = RB Compare has occurred since the last read of the Status Register, if WAVE = 1.
4	TC_CPCS AT91C_TC_CPCS	RC Compare 0 = RC Compare has not occurred since the last read of the Status Register. 1 = RC Compare has occurred since the last read of the Status Register.
5	TC_LDRAS AT91C_TC_LDRAS	RA Loading 0 = RA Load has not occurred since the last read of the Status Register or WAVE = 1. 1 = RA Load has occurred since the last read of the Status Register, if WAVE = 0.
6	TC_LDRBS AT91C_TC_LDRBS	RB Loading 0 = RB Load has not occurred since the last read of the Status Register or WAVE = 1. 1 = RB Load has occurred since the last read of the Status Register, if WAVE = 0.
7	TC_ETRCS AT91C_TC_ETRCS	External Trigger 0 = External trigger has not occurred since the last read of the Status Register. 1 = External trigger has occurred since the last read of the Status Register.

TC: AT91_REG TC_IMR Interrupt Mask Register

TC5 AT91C_TC5_IMR 0xFFFA40AC

TC4 AT91C_TC4_IMR 0xFFFA406C

TC3 AT91C_TC3_IMR 0xFFFA402C

TC2 AT91C_TC2_IMR 0xFFFA00AC

TC1 AT91C_TC1_IMR 0xFFFA006C

TC0 AT91C_TC0_IMR 0xFFFA002C

Offset	Name	Description
0	TC_COVFS AT91C_TC_COVFS	Counter Overflow 0 = No counter overflow has occurred since the last read of the Status Register. 1 = A counter overflow has occurred since the last read of the Status Register.
1	TC_LOVRS AT91C_TC_LOVRS	Load Overrun 0 = Load overrun has not occurred since the last read of the Status Register or WAVE = 1. 1 = RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the Sta-tus Register, if WAVE = 0.
2	TC_CPAS AT91C_TC_CPAS	RA Compare 0 = RA Compare has not occurred since the last read of the Status Register or WAVE = 0. 1 = RA Compare has occurred since the last read of the Status Register, if WAVE = 1.
3	TC_CPBS AT91C_TC_CPBS	RB Compare 0 = RB Compare has not occurred since the last read of the Status Register or WAVE = 0. 1 = RB Compare has occurred since the last read of the Status Register, if WAVE = 1.
4	TC_CPCS AT91C_TC_CPCS	RC Compare 0 = RC Compare has not occurred since the last read of the Status Register. 1 = RC Compare has occurred since the last read of the Status Register.
5	TC_LDRAS AT91C_TC_LDRAS	RA Loading 0 = RA Load has not occurred since the last read of the Status Register or WAVE = 1. 1 = RA Load has occurred since the last read of the Status Register, if WAVE = 0.
6	TC_LDRBS AT91C_TC_LDRBS	RB Loading 0 = RB Load has not occurred since the last read of the Status Register or WAVE = 1. 1 = RB Load has occurred since the last read of the Status Register, if WAVE = 0.
7	TC_ETRCS AT91C_TC_ETRCS	External Trigger 0 = External trigger has not occurred since the last read of the Status Register. 1 = External trigger has occurred since the last read of the Status Register.