AT91 MMU Simple project for AT91RM9200EK - IAR EW ARM

Introduction

The goal of this demonstration project is to show how to initialise cache and MMU on the AT91RM9200EK board. It runs a dhrystone algorithm, caches and MMU enabled/disabled. This program also invokes the AT91 library V3.

Running the application

This application is linked to be loaded and run in FLASH (0x1000_0000). This Download to the target can be done using the JTAG connection.

This very small application sends through the DBGU serial port (115.2Kbps, 8data bits, no parity, 1 stop bit, no flux control J10), messages corresponding to the function name where the printing function has been invoked.

Description

Please refer to the AT91 Simple project for AT91RM9200EK for the description of the initialisation.

The dhrystone algorithm is invoked from the AT91F_Dhrystone (main.c). This function returns how many times the function testloop (dhry_1.c) is called while the CRTR register has not been incremented.

The main program

· calls the AT91F_Dhrystone function caches disabled,

· then Icache enabled (MMU disabled). Obviously performance is rises a lot.

· Then the MMU is initialised calling AT91F_InitMMU (main.c).

o This function reset the level 1 page table entry (located at 0x2001_0000).

o Then it configures 4 entries in this page table:

§ 1MByte section at 0. It must be configured as it is used by the debugger to flush the write cache.

§ 1Mbyte section at 0x5000_0000 it mirrors the physical SDRAM located at 0x1000_0000. This section is cachable.

§ 1Mbyte section at 0x1000_0000. . This is a direct translation: virtual address = physical address. This section is non cachable.

§ 1Mbyte section at 0xFFF0_0000. This is done to access peripheral area. This is a direct translation: virtual address = physical address. This section is non cachable in order to get a direct access to peripheral registers.

o Set the translation table base address register

o Set the domain access register

o And finally enable the MMU

· Dhrystone is then run with only the Icache enabled then with the I + D cache enabled.

The SDRAM is mirrored in order to be able to lock the cache running instructions in a non cachable area. This allows flushing the instruction cache and keeping a strict control while locking perfected instructions. Then the Dhrystone algorithm is run from a cacheable are. This is why the access to the AT91F_Dhrystone function is done through the pDhrystone pointer.

Source files

./init.c	includes low level functions definitions
./main.c	this is the application
./lib_arm920t.h	Inlined functions to drive CP15 register. Should be included in lib_at91rm9200.h ( in the product part of the library)
./mmu.c	Common MMU and Cache operations
/at91_cstartup.s79	cstartup